EE EE 616 Computer Aided Analysis of Electronic Networks Lecture 2 Instructor: Dr. J. A. Starzyk, Professor School of EECS Ohio University Athens, OH, /09/2005

EE Review and Outline Review of the previous lecture -- Class organization -- CAD overview Outline of this lecture * Review of network scaling * Review of Thevenin/Norton Analysis * Formulation of Circuit Equations -- KCL, KVL, branch equations -- Sparse Tableau Analysis (STA) -- Nodal analysis -- Modified nodal analysis

EE Network scaling

EE Network scaling (cont’d)

EE Network scaling (cont’d)

EE V oc Thevenin equivalent circuit Z Th +–+– Norton equivalent circuit Z Th I sc Note: attention to the voltage and current direction Review of the Thevenin/Norton Analysis

EE Pick a good breaking point in the circuit (cannot split a dependent source and its control variable). 2.Replace the load by either an open circuit and calculate the voltage E across the terminals A-A’, or a short circuit A-A’ and calculate the current J flowing into the short circuit. E will be the value of the source of the Thevenin equivalent and J that of the Norton equivalent. 3. To obtain the equivalent source resistance, short-circuit all independent voltage sources and open-circuit all independent current sources. Transducers in the network are left unchanged. Apply a unit voltage source (or a unit current source) at the terminals A-A’ and calculate the current I supplied by the voltage source (voltage V across the current source). The Rs = 1/I (Rs = V). Review of the Thevenin/Norton Analysis

EE Modeling

EE Formulation of circuit equations (cont’d)

EE Ideal two-terminal elements

EE Ideal two-terminal elements Topological equations

EE Determined by the topology of the circuit Kirchhoff’s Current Law (KCL): The algebraic sum of all the currents leaving any circuit node is zero. Kirchhoff’s Voltage Law (KVL): Every circuit node has a unique voltage with respect to the reference node. The voltage across a branch e b is equal to the difference between the positive and negative referenced voltages of the nodes on which it is incident KVL and KCL

EE Unknowns – B branch currents(i) – N node voltages(e) – B branch voltages(v) Equations – KCL: N equations – KVL: B equations – Branch equations: B equations Formulation of circuit equations (cont’d)

EE Determined by the mathematical model of the electrical behavior of a component – Example: V=R·I In most of circuit simulators this mathematical model is expressed in terms of ideal elements Branch equations

EE Matrix form of KVL and KCL N equations B equations

EE K v v + i = i s B equations Branch equation

EE j B 12iN12iN branches nodesnodes (+1, -1, 0) { A ij = +1 if node i is terminal + of branch j -1 if node i is terminal - of branch j 0 if node i is not connected to branch j PROPERTIES A is unimodular 2 nonzero entries in each column Node branch incidence matrix

EE – Sparse Table Analysis (STA) Brayton, Gustavson, Hachtel – Modified Nodal Analysis (MNA) McCalla, Nagel, Roher, Ruehli, Ho Equation Assembly for Linear Circuits

EE Sparse Tableau Analysis (STA)

EE Advantages and problems of STA

EE Write KCL A·i=0 (N equations, B unknowns) 2.Use branch equations to relate branch currents to branch voltages i=f(v)(B unknowns  B unknowns) 3. Use KVL to relate branch voltages to node voltages 4. v=h(e)(B unknowns  N unknowns) Y n e=i ns N equations N unknowns N = # nodesNodal Matrix Nodal analysis

EE Nodal analysis

EE Spice input format: Rk N+ N- Rkvalue N+ N- N+ N- N+ N- i RkRk KCL at node N+ KCL at node N- Nodal analysis – Resistor “Stamp”

EE Spice input format: Gk N+ N- NC+ NC- Gkvalue NC+ NC- N+ N- N+ N- GkvcGkvc NC+ NC- +vc-+vc- KCL at node N+ KCL at node N- Nodal analysis – VCCS “Stamp”

EE Nodal analysis- independent current sources “stamp”

EE Rules (page 36): 1. The diagonal entries of Y are positive and admittances connected to node j 2. The off-diagonal entries of Y are negative and are given by admittances connected between nodes j and k 3. The jth entry of the right-hand-side vector J is currents from independent sources entering node j Nodal analysis- by inspection

EE Example of nodal analysis by inspection: (handout) Example 1 Page 35 ~ 36. Example 2: inspection for networks with VCTs Page 40 ~ 41.

EE Nodal analysis (cont’d)

EE Modified Nodal Analysis (MNA)

EE Modified Nodal Analysis (2)

EE Modified Nodal Analysis (3)

EE General rules for MNA

EE Example 4.4.1(p.143)

EE Advantages and problems of MNA

EE Analysis of networks with VVT’s & Op Amps

EE Example (p.145)

EE Example (p. 148)

EE Example (cont’d)