CMOS VLSI For Computer Engineering Lecture 4 – Logical Effort Prof. Luke Theogarajan parts adapted form Harris – and Rabaey- des.htm Prof. Luke Theogarajan parts adapted form Harris – and Rabaey- des.htm

CMOS VLSI for Computer Engineering How to optimally size gates to minimize delay Need a mathematical way of looking at the problem Consider the following inverter circuit The delay is given by ≅ 0 for short wires

CMOS VLSI for Computer Engineering For any gate define intrinsic input to output capacitance ratio as If we scale the device by S then

CMOS VLSI for Computer Engineering Delay as a function of S S Delay Delay of driver goes up! So there must be an optimum

CMOS VLSI for Computer Engineering Path delay Need to look at overall path if delay optimization is desired, consider N inverters, The delay of any inverter i is given by: N1 CLCL Also C N+1 = C L

CMOS VLSI for Computer Engineering Optimal delay For optimal delay set Collect terms due to C i and differentiate Total path delaywith C N+1 = C L

CMOS VLSI for Computer Engineering Optimal Delay Optimal delay occurs when the size is the geometric mean of the neighbors! The above equation can be satisfied when each gate is sized h times its driver since h is called the fanout of the gate

CMOS VLSI for Computer Engineering Optimal Delay for a chain of inverters If we want to size purely based on final load then define

CMOS VLSI for Computer Engineering Can we generalize to any gate? If we size all gates to be have equivalent resistance of the inverter the R eq stays the same. However the C int increases