1 8 Bit ALU Rahul Vyas Gyanesh Chhipa Jaimin Shah Advisor: Dr. David W. Parent 05/08/2006

2 Abstract The 8-bit ALU that our group designed can perform 8 arithmatic function and 4 logic function The 8s-bit ALU is made up of 2 identical 4- bit ALU, and 25 DFFs. We designed an 8-bit carry look ahead adder that operated at 200 MHz

3 Introduction An ALU is the fundamental unit of any computing system. Understanding how an ALU is designed and how it works is essential to building any advanced logic circuits. Using this knowledge and experience, we can move on to designing more complex integrated circuits. Design consists of different kinds of logic… Look ahead carry generator, adder, Subtractor, Transfer Data, DFF, Multiplexer, Inv, and, Xor, etc

4 Project Summary Created Schematic Tested the schematics logic by using NCVerilog. Finding longest path Sizing of Wn and Wp Layout of individual block Checked DRC and LVS for each block Integrated every block Checked DRC and LVS for final layout Verify the timing Measure power

5 Block diagram of our project ARITHMETIC CIRCUIT LOGICAL CIRCUIT DFF’S MUX DFF’S

6 Project Details [1][1]SELECTIONOUTPUTFUNCTION S2S1S0CIN 0000F=ATransfer A 0001F=A+1Increment A 0010F=A+BAddition 0011F=A+B+1Add with Carry 0100F=A-B-1Substract with Borrow 0101F=A-BSubstraction 0110F=A-1Decrement A 0111F=ATransfer A 100X F=A  B OR 101X F=A  B XOR 110X F=A  B AND 111XF=ĀComplement A [1][1] A=B=8 Bit Inputs. S2 S1,S0,CIN:-Selection Lines

7 Gate level schematic of our circuit

8 Transistor Level Schematic

9 NC VERILOG VERIFICATION

10 Longest path in the circuit

11 Longest Path Calculations Note: All widths are in Cm and capacitances in fF Tphl = 5ns/19 = 0.263ns

12 Individual Block Layout

13 Layout

14 Verification

15 Verification LVS The net lists matched

16 Test Bench and Simulations

17 Output Graphs

18 Cost Analysis –verifying logic: 2 weeks –verifying timing: 1 week –Layout: 1weeks –post extracted timing: 5 days

19 Lessons Learned Aspects of design processes Simulation and verification tools Optimize transistor size to meet specification Use instances See Dr. Parent more often to understand the concept fully.

20 Summary Project:  Our 8-Bit ALU has 1520 transistors and 33 terminals.  The circuit can operate up to 250MHz.  Designed a 8-Bit ALU that performs eight arithmetic and four logical functions at 200MHz frequency with setup and hold time 1ns, driving up to 30fF. This circuit can be used as a building block for 16/32-bit ALU. The Logic design can be modified to perform more functions.

21 Acknowledgements Thanks to Professor David Parent for his Guidance And Help Thanks to Cadence Design Systems for the VLSI lab