Lab 1 Calculator Overview CSE Functional Verification SUNY New Paltz

Specification n Calculator has 4 functions: Add Subtract Shift left Shift right n Calculator can handle 4 requests in parallel All 4 requestors use separate input signals All requestors have equal priority Each port must wait for its response prior to sending the next command

Input/Output description c_clk out_resp2 req1_data_in req1_cmd_in out_data1 req4_cmd_in req3_cmd_in req2_cmd_in req4_data_in req3_data_in req2_data_in reset out_data4 out_data3 out_data2 out_resp4 out_resp3 out_resp1 calc_top

Calculator Input Command and Data n I/O Description Input commands: – 0 - No-op – 1 - Add operand1 and operand2 – 2 - Subtract operand2 from operand1 – 5 - Shift left operand1 by operand2 places – 6 - Shift right operand1 by operand2 places Input Data – Operand1 data arrives with command – Operand2 data arrives on the following cycle

Calculator Output Command and Data n Outputs Response line definition – 0 - no response – 1 - successful operation completion – 2 - invalid command or overflow/underflow error – 3 - Internal error Data – Valid result data on output lines accompanies response (same cycle)

Calculator Input/Output timing req1_data_in req1_cmd_in out_data1 out_resp1 Each port must wait for its response prior to sending the next command!

Other information Clocking – When using a cycle simulator, the clock should be held high (c_clk in the calculator model) – The clock should be toggled when using an event simulator such as Model Sim Calculator priority logic – Priority logic works on first come first serve algorithm – Priority logic allows for 1 add or subtract at a time and one shift operation at a time

Calculator Design n Other information (con't) Resets – Hold reset(1:7) to ' 'b at start of testcase for seven cycles. – During the reset period, outputs of the calculator should be ignored Shift operation – Only the low order 5 bits of the second operand are used Arithmetic operations are unsigned

Create a Test plan n What scenarios do we need to verify? ___________________________________________________

On Unix Machine Build the model n mkdir calculator1 n cd calculator1 n vsim Then put the cursor on the ModelSim main window n vlib work n vmap work /home/yang97/verification/cal1/work n vlib stdlogic n vmap stdlogic /home/yang97/verification/cal1/stdlogic n vlib ieee n vmap ieee /opt/apps01/mentor_g/modeltech/ieee n vlib grd_demo n vmap grd_demo /home/yang97/verification/cal1/grd_demo

Check the waveform n Then go to pulldown menu simulate, select simulate. It will pop up a simulate window, chose design model work/demo_top to load up. Return to ModelSim main window pulldown menu View chose Signals then chose your desired signal, use Force to input stimuli. n There are 5+ bugs in the design! n How many can you find by altering the simple testcase?

Sample Do File Create a file *.do, i.e. calc1.do --add wave -r /* add wave /demo_top/reset add wave /demo_top/c_clk add wave /demo_top/error_found add wave /demo_top/req1_cmd_in add wave /demo_top/req1_data_in add wave /demo_top/out_resp1 add wave /demo_top/out_data1 add wave /demo_top/req2_cmd_in add wave /demo_top/req2_data_in add wave /demo_top/out_resp2 add wave /demo_top/out_data2 add wave /demo_top/req3_cmd_in add wave /demo_top/req3_data_in add wave /demo_top/out_resp3 add wave /demo_top/out_data3

Do File (Continue) add wave /demo_top/req4_cmd_in add wave /demo_top/req4_data_in add wave /demo_top/out_resp4 add wave /demo_top/out_data4 force -freeze sim:/demo_top/reset , force -freeze sim:/demo_top/c_clk 0 0, 1 {50 ns} -r 100 force -freeze sim:/demo_top/error_found(0) 0 0 force -freeze sim:/demo_top/error_found(1) 0 0 force -freeze sim:/demo_top/error_found(2) 0 0 force -freeze sim:/demo_top/error_found(3) 0 0 force -freeze sim:/demo_top/req4_cmd_in , , force -freeze sim:/demo_top/req4_data_in 16# , 16#ffffffff 700, 16# , 16#0 900 force -freeze sim:/demo_top/req3_cmd_in , , force -freeze sim:/demo_top/req3_data_in 16# , 16#ffffffff 701, 16# , 16#0 901

Do File (Continue) force -freeze sim:/demo_top/req2_cmd_in , , force -freeze sim:/demo_top/req2_data_in 16# , 16#ffffffff 704, 16# , 16#0 904 force -freeze sim:/demo_top/req1_cmd_in , , force -freeze sim:/demo_top/req1_data_in 16# , 16#ffffffff 705, 16# , 16#0 905 run 2000 You may run your do file from VSIM by typing –do test.do