VLSI Digital System Design Datapath Operations and Ripple-Carry Add.

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Presentation transcript:

VLSI Digital System Design Datapath Operations and Ripple-Carry Add

Structured Design Qualities 1.Hierarchy 2.Regularity 3.Modularity 1.Well-defined interface 4.Locality 1.Information hiding

Magnitude Comparator Example 1.Separate data path from control blocks - = a b Control z Data path Control blocks

Datapath Organization ● Design one bit slice, then replicate it b1b1 a1a1 -= 0mux z1z1 b0b0 a0a0 -= 0mux z0z0 b3b3 a3a3 -= 0mux z3z3 b2b2 a2a2 -= 0mux z2z2 Control Direction of data flow Directions of control flow Data path Control blocks

Full Adder Truth Table ● cabsco = carry out ● s= a ^ b ^ c(1 or 3 inputs high) ● co= ab + ac + bc(2 or 3 inputs high)

Full Adder Equations ● s= a ^ b ^ c(1 or 3 inputs high) ● co= ab + ac + bc(2 or 3 inputs high) = ab + c(a + b) a b c a b co c s a b

Exclusive-Or Pull-Up Network Common Subexpression Elimination ● s = cab + ca'b' + c'a'b + c'ab' (1 or 3 inputs high) a' b' c' a b a c a' b' c' a b a b' c a' b c b' c' a b a b' c a' b

Exclusive-Or Pull-Down Network Common Subexpression Elimination ● s' = ba'c + bac' + b'ac + b'a'c' (0 or 2 inputs high) a' b c a c' a b' a' b c a b c' a b' c a' b' c' a' b c a c' a b' c a' c'

Exclusive-Or Circuit ● s = abc + ab'c' + a'b'c + a'bc' b' c' s a' b c a b' c' a b a c a' b c a c' a b' a'

Carry Pull-Up Network ● co= ab + ac + bc = bc + a(b + c) = ac + b(a + c) = ab + c(a + b) a' b' a' c' b'

Carry Pull-Down Network ● co'= ( a* b+ c*( a+ b ) )' = ( a* b )'*( c*( a+ b ) )' = ( a'+ b' )*( c'+( a+ b )' ) = ( a'+ b' )*( c'+ a'* b' ) a' b' a' b' c'

Carry Circuit ● co= ab + c(a + b) co a' b' a' b' c' a' b' a' c' b'

Full Adder Circuit ● s= abc + ab'c' + a'b'c + a'bc' ● co= ab + c(a + b) b' c' a' b c a co a' b' a' b' c' a' b' a' c' b' s a' b' c' a b a c a' b c a c' a b' a'

Alternative Sum Equation ● cabscoco' ● s= abc + co'(a + b + c)

Alternative Carry Out Circuit ● s= abc + co'(a + b + c) ● cp= co' = ( ab + c(a + b) )' cp a b a b c a b a c b

Alternative Sum Pull-Down Network ● s'= ( abc + cp(a + b + c) )' a b abc cp c

Alternative Full Adder Circuit ● cp'= ( ab + c(a + b) )' ● s'= ( abc + cp(a + b + c) )' a b abc cp c bc a a b c a b a b c a b a c b co s

Ripple-Carry Adder ● Total add time = n*(delay of one FA) b1b1 a1a1 FA b0b0 a0a0 b3b3 a3a3 b2b2 a2a2 s2s2 s1s1 s0s0 s3s3 carry in carry out Critical path

Faster Ripple-Carry Adder ● Delete carry inverter in alternate Fas b1b1 a1a1 b0b0 a0a0 b3b3 a3a3 b2b2 a2a2 s2s2 s1s1 s0s0 s3s3 carry in carry out FA Critical path

Ripple-Carry Subtractor ● a – b = a + (~b) + 1 b1b1 a1a1 FA b0b0 a0a0 b3b3 a3a3 b2b2 a2a2 s2s2 s1s1 s0s0 s3s3 carry in carry out

Ripple-Carry Adder-Subtractor ● Conditionally invert b ● Conditionally assert carry in b1b1 a1a1 FA b0b0 a0a0 b3b3 a3a3 b2b2 a2a2 s2s2 s1s1 s0s0 s3s3 subtract carry out