Processor Design 5Z032 Memory Hierarchy Chapter 7 Henk Corporaal Eindhoven University of Technology 2009

TU/e Processor Design 5Z0322 Topics n Memories: review n Memory Hierarchy: why? n Basics of caches n Measuring cache performance n Improving cache performance n Framework for memory hierarchies n Virtual memory n Pentium Pro and PowerPC 604 memory hierarchies

TU/e Processor Design 5Z0323 n SRAM: u value is stored on a pair of inverting gates u very fast but takes up more space than DRAM (4 to 6 transistors) n DRAM: u value is stored as a charge on capacitor (must be refreshed) u very small but slower than SRAM (factor of 5 to 10) Memories: Review

TU/e Processor Design 5Z Memory Hierarchy, why? n Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns at cost of $5 to $10 per Mbyte. Disk access times are 10 to 20 million ns at cost of $.10 to $.20 per Mbyte. n Try and give it to them anyway u build a memory hierarchy CPU Level 1 Level 2 Level n Size Speed

TU/e Processor Design 5Z0325 Locality n A principle that makes having a memory hierarchy a good idea n If an item is referenced, temporal locality: it will tend to be referenced again soon spatial locality : nearby items will tend to be referenced soon. Why does code have locality? n Our initial focus: two levels (upper, lower) u block: minimum unit of data u hit: data requested is in the upper level u miss: data requested is not in the upper level

TU/e Processor Design 5Z0326 Exploiting locality

TU/e Processor Design 5Z0327 n Two issues: u How do we know if a data item is in the cache? u If it is, how do we find it? n Our first example: u block size is one word of data u "direct mapped" For each item of data at the lower level, there is exactly one location in the cache where it might be. e.g., lots of items at the lower level share locations in the upper level Cache

TU/e Processor Design 5Z0328 n Mapping: address is modulo the number of blocks in the cache Direct Mapped Cache

TU/e Processor Design 5Z0329 n For MIPS: What kind of locality are we taking advantage of? Direct Mapped Cache Byte offset ValidTagDataIndex Tag Index HitData Address (bit positions)

TU/e Processor Design 5Z03210 n Taking advantage of spatial locality: Direct Mapped Cache Address (bit positions)

TU/e Processor Design 5Z03211 n Read hits u this is what we want! n Read misses u stall the CPU, fetch block from memory, deliver to cache, restart the load instruction n Write hits: u can replace data in cache and memory (write-through) u write the data only into the cache (write-back the cache later) n Write misses: u read the entire block into the cache, then write the word (allocate on write miss) u do not read the cache line; just write to memory (no allocate on write miss) Hits vs. Misses

TU/e Processor Design 5Z03212 n Make reading multiple words easier by using banks of memory n It can get a lot more complicated... Hardware Issues

TU/e Processor Design 5Z03213 n Increasing the block size tends to decrease miss rate: Performance

TU/e Processor Design 5Z03214 Performance n Use split caches because there is more spatial locality in code:

TU/e Processor Design 5Z03215 Performance n Simplified model: execution time = (execution cycles + stall cycles)  cycle time stall cycles = # of instructions  miss rate  miss penalty

TU/e Processor Design 5Z03216 Performance T exec = N inst CPI T cycle with CPI = CPI ideal + CPI stall CPI stall = %reads missrate read misspenalty read + %writes missrate write misspenalty write or: T exec = (N normal-cycles + N stall-cycles ) T cycle with N stall-cycles = N reads missrate read misspenalty read + N writes missrate write misspenalty write (+ Write-buffer stalls )

TU/e Processor Design 5Z03217 Performance example n Assume GCC application (pg 311) u Icache missrate 2% u Dcache missrate 4% u CPI ideal is 2.0 u Misspenalty 40 cycles n Calculate CPI CPI = CPIstall CPIstall = Instruction-miss cycles + Data-miss cycles Instruction-miss cycles = Ninstr x 0.02 x 40 = 0.80 Ninstr Data-miss cycles = Ninstr x %ld-st x 0.04 x 40 %ld-st = 36 % Slowdown: 1.68 !!

TU/e Processor Design 5Z03218 Performance example (cont’d) What if ideal processor had CPI = 1.0 (instead of 2.0) n Slowdown would be 2.36 ! What if processor is clocked twice as fast n => penalty becomes 80 cycles n CPI = 4.75 n Speedup = N.CPIa.Tclock / (N.CPIb.Tclock/2) = 3.36 / (4.75/2) n Speedup is not 2, but only 1.41 !!

TU/e Processor Design 5Z03219 Improving performance n Two ways of improving performance: u decreasing the miss ratio: associativity u decreasing the miss penalty: multilevel caches What happens if we increase block size?

TU/e Processor Design 5Z03220 Decreasing miss ratio with associativity block 2 blocks / set 4 blocks / set 8 blocks / set

TU/e Processor Design 5Z03221 An implementation: 4 way associative

TU/e Processor Design 5Z03222 Decreasing miss ratio with associativity Exercise n Compared to direct mapped, give a series of references that: u results in a lower miss ratio using a 2-way set associative cache u results in a higher miss ratio using a 2-way set associative cache assuming we use the “least recently used” (LRU) replacement strategy

TU/e Processor Design 5Z03223 Performance 1 KB 2 KB 8 KB

TU/e Processor Design 5Z03224 Decreasing miss penalty with multilevel caches n Add a second level cache: u Often primary cache is on the same chip as the processor u Use SRAMs to add another cache above primary memory (DRAM) u Miss penalty goes down if data is in 2nd level cache n Example: u Base CPI of 1.0 on a 500Mhz machine with a 5% miss rate, 200ns DRAM access u Adding 2nd level cache with 20ns access time decreases miss rate to 2% Q. How much faster will this machine become? n Using multilevel caches: u Try and optimize the hit (access) time on the 1st level cache u Try and optimize the miss rate on the 2nd level cache

TU/e Processor Design 5Z03225 The illusion of one big (protected) memory

TU/e Processor Design 5Z03226 Why virtual memory n Each program has a separate address space n Protection u Read-only pages u Executable pages u Shared pages n Illusion of big memory n Supported by MMU: memory management unit

TU/e Processor Design 5Z03227 Memory organization n The operating system, together with the MMU hardware, take care of separating the programs. n Each program runs in its own ‘virtual’ environment, and uses logical addressing that is (often) different the the actual physical addresses. n Within the virtual world of a program, the full 4 Gigabytes address space is available. (Less under Windows) n In the von Neumann architecture, we need to manage the memory space to store the following: u The machine code of the program u The data: F Global variables and constants F The stack/local variables F The heap Main memory Program + Data

TU/e Processor Design 5Z03228 Memory Organization: more detail Machine code 0x xFFFFFFFF Global variables Stack Heap The program itself: a set of machine instructions. This is in the.exe Before the first line of the program is run, all global variables and constants are initialized. The local variables in the routines. With each routine call, a new set of variables if put in the stack. Free memory The memory that is reserved by the memory manager If the heap and the stack collide, we’re out of memory Stack pointer Fixed size Fixed size Variable size Variable size

TU/e Processor Design 5Z03229 Physical address Memory management n Problem: many programs run simultaneously n MMU manages the memory access. Main memory CPU Memory Management Unit Cache memory Logical address Swap file on hard disk 2K block Process table Each program thinks that it owns all the memory. Physical address Virtual Memory Manager Checks whether the requested address is ‘in core’ Physical address Yes: No: load 2K block from swap file on disk Yes: No: access violation

TU/e Processor Design 5Z03230 Virtual Memory n Main memory can act as a cache for the secondary storage (disk) virtual memory physical memory n Advantages: u illusion of having more physical memory u program relocation u protection

TU/e Processor Design 5Z03231 Pages: virtual memory blocks n Page faults: the data is not in memory, retrieve it from disk u huge miss penalty, thus pages should be fairly large (e.g., 4KB) u reducing page faults is important (LRU is worth the price) u can handle the faults in software instead of hardware u using write-through is too expensive so we use writeback

TU/e Processor Design 5Z03232 Page Tables

TU/e Processor Design 5Z03233 Page Tables

TU/e Processor Design 5Z03234 Size of page table n Assume u 40-bit virtual address; 32-bit physical u 4 Kbyte pages; 4 bytes per page table entry n Solution u Size = N entries * Size-of-entry = 2 40 / 2 12 * 4 bytes = 1 Gbyte n Reduce size: u Dynamic allocation of page table entries u Hashing: inverted page table u 1 entry per physical available instead of virtual page u Page the page table itself (i.e. part of it can be on disk) u Use larger page size (multiple page sizes)

TU/e Processor Design 5Z03235 Making Address Translation Fast n A cache for address translations: translation lookaside buffer (TLB)

TU/e Processor Design 5Z03236 TLBs and caches Yes Deliver data to the CPU Write? Try to read data from cache Write data into cache, update the tag, and put the data and the address into the write buffer Cache hit?Cache miss stall TLB hit? TLB access Virtual address TLB miss exception No YesNo YesNo Write access bit on? Yes No Write protection exception Physical address

TU/e Processor Design 5Z03237 Overall operation of memory hierarchy n Each instruction or data access can result in three types of hits/misses: TLB, Page table, Cache n Q: which combinations are possible? Check them all! TLBPage tableCachePossible? hit Yes, but..... hit miss hitmisshit miss hit misshitmiss hit miss

TU/e Processor Design 5Z03238 Modern Systems n Very complicated memory systems u multiple levels of cache u separate L1 data and instruction caches u writeback buffer u prefetching u hit under miss u.... n Virtual memory examples:

TU/e Processor Design 5Z03239 Modern Systems Pentium Pro dual chip module n First level Cache organization

TU/e Processor Design 5Z03240 Common framework for memory hierarchies Answer the following 4 questions for each memory level (registerfile, Li-cache, virtual memory) n Q1: where can a block be placed? n Q2: how is a block found? n Q3: wich block should be replaced on a miss? n Q4: what happens on a write? Let’s answer this for a cache (try yourself for registers and virtual memory)

TU/e Processor Design 5Z03241 Common framework for memory hierarchies Q1: where can a block be placed? u note: a block is in this case a cache line n Direct mapped cache: one position n n-way set-associative cache: n positions (typically 2-8) n Fully associative: everywhere Q2: how is a block found? n Direct mapped: index part of address indicates entry n n-way: use index to search in all the n cache blocks n Fully associative: check all tags

TU/e Processor Design 5Z03242 Common framework for memory hierarchies Q3: wich block should be replaced on a miss? n Direct mapped: no choice n Associative caches: use replacement algorithm, like LRU Q4: what happens on a write? n write-through  write-back n on a write miss: allocate  no-allocate write-throughwrite-back no-allocate on write miss allocate on write miss Q: Which combinations make sense?

TU/e Processor Design 5Z03243 Common framework for memory hierarchies n Understanding (cache) misses:The three Cs n Compulsory miss n Capacity miss n Conflict miss cache size miss rate direct mapped (1-way) 2-way fully associative compulsory capacity 4-way

TU/e Processor Design 5Z03244 n Processor speeds continue to increase very fast u much faster than either DRAM or disk access times Future n Design challenge: dealing with this growing disparity n Trends: u SDRAM, DDR, RambusDRAM,... u restructure code to increase locality u use prefetching (make cache visible to ISA) Performance Year 35 %/y Memory 7 %/y 55 %/y Processing Performance gap 10

TU/e Processor Design 5Z03245 Exercises From Chapter seven: n 7.2, 7.3 n n 7.20, 7.21 n 7.27, 7.32