Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Chapter #6: Sequential Logic Design Sequential Switching Networks

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Simple Circuits with Feedback Simple memory elements created from cascaded gates Simplest gate component: inverter Basis for commercial static RAM designs Cross-coupled NOR gates and NAND gates also possible These two types of memory elements form the basic building blocks of the latch and flip-fllop memory elements

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Simple Circuits with Feedback 1. Cascaded Inverters: (a) Static Memory Cell "0" "1" Selectively break feedback path to load new value into cell. CMOS transmission gates are used to implement a 2:1 MUX on the inputs to the memory element. When LD (load) is asserted, the feedback path is broken and the value at input A can be stored in the element. When LD is unasserted, the input from A is broken, and feedback path is reasserted. Many logic simulators have difficulty modeling these signal flows because of the critical nature of the timing of the signals in these kinds of circuits.

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Inverter Chains -- (b) Ring Oscillators Odd # of stages leads to ring oscillator Snapshot taken just before last inverter changes Repeats every tp time units --- period Duty cycle -- percentage of time a signal is high during the period Output high propagating thru this stage Timing Waveform: A (=X) B C D E Period of Repeating Waveform (tp) Gate Delay (td) tp = 2n * td n = # inverters each node stays low or high for exactly 5 gate delays

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Inverter Chains Propagation of Signals through the Inverter Chain

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks 2. Cross-Coupled NOR (or NAND) Gates as a basic Memory Element R R S S Q \Q R = 1 and S=0, Q output is reset to 0, Q’=1 R = 0 and S = 1, Q is set to 1, Q’ =0. R = 0 and S = 0, outputs hold their current vals -- Q=0, Q’ =1 R - Reset input, S -- Set input ==> R-S latch Just like cascaded inverters, with capability to force output to 0 (reset) or 1 (set) Two alternatives to represent cross-coupled NORs. R-S Latch R S Q Q’

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Timing Waveform Reset Hold Set Forbidden State ResetSet Forbidden State Race When R=S=0, the NOR gates behave like invertors, switching the outputs back to 0. This oscillatory behavior is called race condition.

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks State Behavior of R-S Latch Truth Table Summary of R-S Latch Behavior - - reset -- set

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Logic Networks Theoretical R-S Latch State Diagram State Diagram: node - repr state of the circuit arc - labeled with input combinations that cause a transition from one state to another ResetSet Hold

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Logic Networks Observed R-S Latch Behavior Very difficult to observe R-S Latch in the 11 state Ambiguously returns to state 01 or 10 A so-called "race condition" Reset Set

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Definition of Terms Setup Time (Tsu) Clock: Periodic Event, causes change from current state to next state rising edge, falling edge, high level, low level There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Output of a sequential circuit is a function of the current inputs and any signals that are fed back to the inputs. Feedback signals are called the current state.

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Latches vs. Flipflops Input/Output Behavior of Latches and Flipflops Type When Inputs are Sampled When Outputs are Valid unclocked always propagation delay from latch input change level clock high propagation delay from sensitive (Tsu, Th around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (Tsu, Th around falling edge of clock falling clock edge) Primitive memory elements fall into two classes: latches and flip-flops

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Level-Sensitive Latch Schematic: aka Gated \R-\S Latch R=S=1hold state R=S=0forbidden state R’ = 1, S’=0set R’=0, S’=1reset Enable signal is active low. When it is high the outputs are in a holding state. R S Q 0 0 unstable reset set 1 1 hold

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Bubble here if negative edge triggered device Timing Diagram: Behavior the same unless input changes while the clock is high Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock is asserted D Clk Q Q Output ‘Q’ = Input ‘D’ Q+ = D

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Elements Typical Timing Specifications: Flipflops vs. Latches 74LS74 Positive Edge Triggered D Flipflop Setup time Hold time Minimum clock width Propagation delays (low to high, high to low, max and typical) All measurements are made from the clocking event that is, the rising edge of the clock

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Typical Timing Specifications: Flipflops vs. Latches 74LS76 Transparent Latch Setup time Hold time Minimum Clock Width Propagation Delays: high to low, low to high, maximum, typical data to output clock to output Measurements from falling clock edge or rising or falling data edge

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Elements R-S Latch Revisited Truth Table: Next State = F(S, R, Current State) Derived K-Map: Characteristic Equation: Q+ = S + R Q t Qt = Q(t +  ) HOLD RESET SET NOT ALLOWED

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks J-K Latch How to eliminate the forbidden state of the R-S latch? Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle Characteristic Equation: Q+ = Q K + Q J HOLD RESET SET TOGGLE JK Q(t)

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks J-K Latch: Race Condition Set Reset Toggle Race Condition Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop Since toggle values of J,K = 11 remain asserted to RS while the output is changing, thus flipping the value of RS presented to internal latch, causing it to toggle again (continues until toggle removed).

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Network Master/Slave J-K Flipflop Master Stage Slave Stage Sample inputs while clock high Sample inputs while clock low Uses time to break feedback path from outputs to inputs!

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Network Master/Slave J-K Flipflop Correct Toggle Operation

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Edge-Triggered Flipflops 1's Catching: a glitch on the J or K inputs leads to a state change! forces designer to use hazard-free logic Solution: edge-triggered logic (sample inputs only on rising or falling clock edge) Negative Edge-Triggered D flipflop 4-5 gate delays setup, hold times necessary to successfully latch the input Characteristic Equation: Q+ = D Negative edge-triggered FF when clock is high Now have problem of 1’s catching.

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Network Edge-triggered Flipflops Step-by-step analysis Negative edge-triggered FF when clock goes high-to-low data is latched Negative edge-triggered FF when clock is low data is held If D=1, R-S latch sets If D=0, R-S latch resets Changes to 0, gates 2,4,5 hold their previous values D changes

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks Positive vs. Negative Edge Triggered Devices Positive Edge Triggered Inputs sampled on rising edge Outputs change after rising edge Negative Edge Triggered Inputs sampled on falling edge Outputs change after falling edge

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Toggle Flipflop Single input that causes the stored state to be complemented when the input is asserted. Not normally found in stardard parts catalogs because they are so easy to construct from other flip flops Formed from J-K with both inputs wired together Sequential Switching Networks J K Q Q’ T J K Q Q T Q Q

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No Sequential Switching Networks

Contemporary Logic Design Sequential Logic © R.H. Katz Transparency No HW #12 -- Section 6.1