A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation Viet L. Do and Kenneth Y. Yun IEEE Transactions on Circuits and Systems for Video Technology, Vol.8, No.4, Aug 1998

Outline Introduction Full-Search Block-Matching Process Conservative Approximation Low-Power VLSI Architecture Simulation Results Conclusion

Introduction Motion compensation technique reduce the coding bit-rate by eliminating temporal redundancy in video sequences The full-search algorithm exhaustively checks all candidate blocks to find the best match within a particular window Proposed method computes a conservative estimate of the exact distortion value for each candidate macroblock before computing the exact distortion

Full-Search Block-Matching Process

Conservative Approximation (1) Conservative estimate of D(u, v) Partial estimate for the ith row of candidate macroblock (u, v)

Conservative Approximation (2)

Low-Power VLSI Architecture

Processing Element Array (1)

Processing Element Array (2)

Processing Element Array (3) Size of search area is (N+2w) 2, but only (2w+1) 2 candidate blocks are valid Need (N+2w-1)(N-1)+N cycles for initialization, and N-1 cycles for shift to next row

Block-Matching Unit

Distortion Approximation Unit

Simulation Results (1) Define a new measure of energy consumption: one unit of ADE (absolute difference equivalent) is the amount of energy consumed in computing one AD One AD calculation is roughly equivalent to two additions Calculating D(u, v) consumes 1.5N 2 ADE Computing PD i ^(u+1, v) consumes ADE on average Thus computing D^(u+1, v) consumes ADE Therefore, the energy consumption for computing D^(u+1,v) is linear in N whereas the energy consumption for computing D(u,v) is quadratic in N

Simulation Results (2) Correlation: the pixels in the same relative positions of two consecutive candidate blocks have the same luminance values Taking correlation into account, it reduces to 0.85* = 346 ADE Low-power architecture implementation requires *346 = 192 ADE Only 192/346 = 55% of that of conventional systolic architecture

Simulation Results (3)

Conclusion The conservative approximation method that reduces power consumption in full- search block-matching motion estimation Simulation results show that the proposed low-power VLSI architecture consumes half as much power as the conventional systolic array based architecture