Status of OTIS development Outer Tracker meeting LHCb week, 2001, may 7 – may 11 Harald Deppe, Martin Feuerstack-Raible, Uwe Stange, André Srowig Heidelberg.

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Presentation transcript:

Status of OTIS development Outer Tracker meeting LHCb week, 2001, may 7 – may 11 Harald Deppe, Martin Feuerstack-Raible, Uwe Stange, André Srowig Heidelberg University

OTIS submission overview zDLL1.0, submitted september 2000, measurements in work (partly presented here) yFirst DLL prototype, contains x32 stage delay chain with 32 taps xMean delay per stage = 781ns nominal zOTISDLL1.0, submitted february 28, 2001 y2nd DLL prototype, contains x32 stage delay with 64 taps xMean delay per tap = 390ns nominal zOTISMEM1.0, submitted february 28, 2001 yContains rad hard L0 pipeline & derandomizer memory x32 channels * (1 + 6)bit/ch bit = 240bit wide x186 bit long

DLL1.0 measurements(1) zLock time is well below 2  s Accidentally the lock gets lost and the DLL needs a reset yNot yet understood, maybe a problem in the test setup (e. g. switching on a neighbouring monitor causes loss of lock state), but operation of several hours w/o problems also possible. Voltage controlling delay settles 2µs after reset of the circuit

DLL1.0 measurements (2) zLock range = 22…44MHz at 300K ySpec is 30…50MHz at 300K. yThis is fully understood xan old W/L extraction rule for the transistors was used when the design was done xusing the old layout with the new extraction rules yields an simulated lock range 20…40MHz (within an 10% error) xOTISDLL1.0 layout has been corrected for lock range within specs

DLL1.0 measurements (1) zDifferential non-linearity (DNL) y1.9bins at 40MHz xLarge due to non-controlled dummy delay before first delay tap y0.58bins at 30MHz (in the middle of the actual lock range, which fits better with the dummy delay) zThis translates to a resolution of y1.482ns at 40MHz y0.604ns at 30MHz zExtrapolation to OTISDLL1.0 yDNL = 0.58bins at 40MHz => resolution 0.45ns (within spec) f = 40MHz f =30MHz

Next steps zOTISDLL1.0 and OTISMEM1.0 expected back in july 2001 yDetailed measurements will be done asap zCurrently working on ybehavioral model of the components yOverall design of chip OTIS1.0 zExpect specification workshop in june