S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 26: Project Overview Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Project Overview Objective: Design an 8-bit subset of a MIPS microprocessor 32-bit instruction encoding 8 registers $0-$7 (Register $0 is hardwired to be 0) An 8-bit counter (PC) 10 instructions

S. Reda EN160 SP’07 MIPS instruction set

S. Reda EN160 SP’07 Instruction format

S. Reda EN160 SP’07 Example program (required testbench) compile

S. Reda EN160 SP’07 Example program (required testbench) Translate

S. Reda EN160 SP’07 MIPS organization

S. Reda EN160 SP’07 Controller is a FSM that controls the CPU Controller generates multiplexer select signals and register enables to sequence the datapath

S. Reda EN160 SP’07 ALU control

S. Reda EN160 SP’07 Logic Design Each read/write takes four cycles to read 32 bits from the memory

S. Reda EN160 SP’07 Block diagram

S. Reda EN160 SP’07 Main parts

S. Reda EN160 SP’07 Main tasks Controller FSM (2) ALU (2) Register file (2) ALU control (1) Integration/Memory/simulating the program (2)

S. Reda EN160 SP’07 Timeline TaskDeadline standard libraryApril 9/11 Defining each unit interface clearly (inputs/outputs). Documents sent to integrator. April 13 Design of each unit finalized and sent to integrator April 23 Design Integrated and simulated April 27

S. Reda EN160 SP’07 Requirements for each design you submit Please include all the following when you submit to the integrator. Standard cells (verified w power/area/timing numbers) (2 points) Prototype IC layout included (6 points) Include functional design verification (7 points) Describe how did you optimize/constrain your design in terms of area/time/power/reliability (5 points)?