Performed by: Gerber Alex, Koren Chen. Instructor: Mony Orbach המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט ( סופי ) Subject: Smart home using Bluetooth Access Point + EndPoint Project name: Asgard סמסטר חורף – אביב,

Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Creating a Smart House. A smart wireless network that can be spread out all across the house. Controlling endpoints (home appliances) or gathering data (pictures from a camera, sound from a telephone). Automatic addition of endpoints to the network. (Without the need for special configuration). Maximum flexibility when attaching to endpoints. Using the Bluetooth wireless protocol.

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Asgard Application Bluetooth Unit Computer Bluetooth Unit Asgard Access Point Bluetooth Unit

Asgard Card Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 RS232 IF MAX232 FPGA Flex10K10 0 Connect or Dtype(9 pins) Generic Application Through Flat Cable – 50 pin USB Controller SL811 Connect or USB – Type A

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware A printed circuit board containing a dedicated bluetooth CPU implemented on an FPGA, integrated with smart peripherals. CPU type: CISC based with special commands added for HCI support. Integrated RAM, ROM, UART for RS232, USB controller interface. Support for bluetooth radio cards of Ericsson and Philips. Software Asgard operating system is divided into two: Access point OS (automatic discovery of bluetooth endpoints, and creates a personal area network (PAN)). Endpoint OS (waits for request for connection, implements a specific application – e.g. LCD display). Both can be run on the same hardware!!! Complete development environment containing: Assembler, linker. 4

FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Execution unit (EXE) Registers Instruction Decode And Fetch Unit (IDF) opcode Memory Data Memory Arithmetic Logic Unit (ALU) I/O (RS232 + USB + Generic App)

A real life example המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Asgard AP