03/08/2005 © J.-H. Jiang1 Retiming and Resynthesis EECS 290A – Spring 2005 UC Berkeley

2 Outline Motivations Retiming & resynthesis An optimization perspective Peripheral retiming Transformation power A verification perspective Verification complexity

3 Why retiming & resynthesis? Sequential optimization Go beyond purely combinational minimization Combinational synthesis cannot cross register boundaries Retiming & resynthesis Retiming: redefine register boundaries by pushing/pulling registers around Resynthesis: minimize combinational logics Optimize sequential networks using combinational techniques Avoid expensive computation Note that clock skewing does not support resynthesis

4 Retiming Retiming for combinational optimization Redefine a register boundary such that the combinational block subject to optimization is as large as possible Peripheral retiming [MSBS91] extends this idea one step further Allow “negative” registers (negative weights on edges of a communication graph) Borrow registers from the environment Need to be able to eliminate negative registers at the end of the optimization (but no need for verification purpose [KB01]) Return registers to the environment Allow “negative” registers exist only on peripheral edges of a circuit graph

5 Resynthesis Rewrite circuit structures in any way while maintaining the functionalities of transition/output functions E.g., simplification, decomposition, Boolean resubstitution, etc. [DeM91]

6 Retiming & resynthesis on pipelined circuits Introduce negative registers, if necessary, to enlarge the combinational block In theory, no need to have iterative retiming & resynthesis if all the latches can be pushed to the peripheral edges Two retimings and one resynthesis are enough

7 Retiming & resynthesis on FSMs Retiming & resynthesis on FSMs can achieve any state re-encoding [Mal90] In theory, iterating retiming & resynthesis may produce different (but equivalent) STGs which cannot be produced by one retiming & one resynthesis

8 What retiming & resynthesis can do Re-encoding How about any equivalent transformations on STGs? (Orthogonal to the state encoding problem) STGs of an FSM are not canonical (but equivalent) Given any two equivalent STGs, can retiming & resynthesis transform one to the other?

9 What retiming & resynthesis cannot do An example where retiming & resynthesis fail G1 and G2 are not transformable to each other under retiming and resynthesis

10 State immediate equivalence Definition. Two states are immediately equivalent if, under any input assignment, they have the same next state and output valuation

11 Effects of an atomic backward move An atomic backward move of retiming can split a state into several immediately equivalent states and/or annihilate states which have no predecessor state

12 Effects of an atomic forward move An atomic forward move of retiming can merge immediately equivalent states to one state and/or create states which have no predecessor state

13 Transformation power of iterative retiming & resynthesis Two STGs are transformable to each other under retiming & resynthesis if and only if there exists a sequence of splitting a state into imm. eq. states, and merging imm. eq. states to a state which changes one STG to the other [Ran97, RSSB98] Resynthesis does not change an STG We ignore the set of unreachable dangling states created by forward moves of retiming (In the next lecture, we will see that these states have decisive effects on initialization sequences)

14 How to tell equivalence under retiming & resynthesis Given two STGs, how do we tell if they are transformable to each other under retiming & resynthesis? Canonical representation for STGs which are equivalent under retiming & resynthesis?

15 State minimization under immediate equivalence Algorithm: STG minimization under immediate equivalence Input: an STG Output: minimized canonical STG 1. Remove dangling states (not strongly connected) 2. Repeat 3. Merge all immediately equivalent states 4. Until no merging can be performed 5. Return the minimized STG

16 Equivalence under retiming & resynthesis Two STGs are equivalent under retiming & resynthesis if they have isomorphic minimized representations derived from the previous procedure

17 Optimization power of peripheral retiming plus resynthesis Can peripheral retiming (in combination with resynthesis) bring in more optimization power than standard retiming? In theory, no; in practice, yes Edges with negative weights cannot be removed by resynthesis

18 Verification – Rt Graph isomorphism checking (with known input/output correspondence) Circuit graph (except weights on edges) is unchanged under retiming Loop invariant checking Register count of every cycle in a circuit graph must be unchanged under retiming Only need to check fundamental cycles (linearly independent cycle set) O(|E| 2 log|V|) [SSBS92] Poly-time solvable

19 Verification – Rt + Rs Assume transformation history unknown Search the right register boundary (in the original circuit) How many such boundaries are possible? Check combinational equivalence for each boundary configuration NP-complete

20 Verification – Rt + Rs + Rt Assume transformation history unknown Search the right register boundaries (in both the original and modified circuits) Check combinational equivalence for each boundary configuration NP-complete

21 Verification – Rt + Rs + Rt + Rs Assume transformation history unknown May not have corresponding register boundary In fact, (Rs + Rt + Rs) is already non-trivial Complexity? There are infinitely many (countable) possibilities in rewriting circuits by resynthesis  2 [Ran97] (but very unlikely)

22 Verification – (Rt + Rs)* Assume transformation history unknown In fact, PSPACE-complete Same as general sequential equivalence checking The foregoing algorithm on checking equivalence under retiming & resynthesis only tells us an upper bound of the verification complexity (polynomial in the number of states, exponential in the number of state bits)

23 Circumventing the hardness Need transformation history, or Check equivalence step by step along the retiming/resynthesis transformation

24 Conclusions We learned the transformation power of retiming & resynthesis, and its verification complexity We will discuss the initialization of synchronous systems, including how initialization sequences are affected by retiming & resynthesis

25 References [DeM91] G. De Micheli. Synchronous logic synthesis: algorithms for cycle-time minimization. IEEE Trans. CAD, [J05] J.-H. Jiang. On some transformation invariants under retiming and resynthesis. In Proc. TACAS, [KB01] A. Kuehlmann & J. Baumgartner. Transformation-based verification using generalized retiming. In Proc. CAV, [Mal90] S. Malik. Combinational Logic Optimization Techniques in Sequential Logic Synthesis. PhD thesis, UC Berkeley, [MSBS91] S. Malik, E. Sentovich, R. Brayton & A. Sangiovanni-Vincentelli. Retiming and resynthesis: optimization of sequential networks with combinational techniques. IEEE Trans. CAD, [Ran97] R. Ranjan. Design and Implementation Verification of Finite State Systems. PhD thesis, UC Berkeley, [RSSB98] R. Ranjan, V. Singhal, F. Somenzi & R. Brayton. On the optimization power of retiming and resynthesis transformations. In Proc. ICCAD, [SSBS92] N. Shenoy, K. Singh, R. Brayton and A. Sangiovanni-Vincentelli, On the temporal equivalence of sequential circuits. In Proc. DAC, [ZSA98] H. Zhou, V. Singhal & A. Aziz. How powerful is retiming? In Proc. IWLS, 1998.