King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 1 COE 308 Building the Datapath

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 2 COE 308 Definitions The processor executes instructions that operate on data. Data is modified, moved, produced and discarded as a result of the program’s target The Datapath is the hardware circuitry of the processor where the Data is: –Temporarily stored –Modified By opposition, the Control Unit is responsible for controlling and monitoring the Datapath to ensure the proper execution of the instructions

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 3 COE 308 Digital Circuit Model Combinational Logic Memorization Elements A Digital Circuit is modeled as a Sequential Circuit It consists of several Memorization Elements connected to one another through combinational logic blocks. The Memorization Elements are governed by clocking signals defined by a clocking methodology Inputs of any combinational logic block come from memorization elements and are fed-back into memorization elements

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 4 COE 308 Clocking Methodology Use an edge-triggered clocking methodology D Ck Q DQ t+1 ↑ 00 ↑ 11 0/1/↓-QtQt -QtQt Memorization elements values are only updated on the active edge of the clock Memorization elements outputs are available immediately after their update and stable for the whole duration of the clock cycle Combinational Logic Input Ck Output Memorization Element Delay Combinational Logic Delay No infinite loop using edge-triggered Memorization Elements

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 5 COE 308 General Design Methodology Clearly understand the list of requirements Translate the requirements list into design-oriented requirements that can be directly mapped into design blocks Divide the design into several design blocks organized by function that implement the list of requirements Clearly define the inputs and outputs of each block (interface) Connect the blocks together to form the design entity as a whole Refine the details by verifying that each item in the requirement list is fully fulfilled. Add the necessary modifications if needed.

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 6 COE 308 Requirements To simplify the design, only a subset of the MIPS instruction set is to be supported by the datapath. The subset consists of the following instructions: –Arithmetic and Logic instructions Add, Sub, And, Or and Slt –Both Register and Immediate addressing modes are included –Memory Access Instructions Lw and Sw –Control Sequence instructions: branch if equal (Beq) Start with a simple implementation that uses a single clock cycle for every instruction

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 7 COE 308 Single Clock Cycle Model Combinational Logic State Element In a single clock cycle execution model: Every instruction is executed in a single clock cycle The state elements are modified at the end of the execution of each instruction. Means: –Datapath architecture should not have intermediate registers to store partial results in the middle of the execution of one instruction Instruction Flow Ck Instruction i-1Instruction iInstruction i+1Instruction i+2

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 8 COE 308 How to Proceed Need to implement a Datapath that executes 3 types of instructions: Arithmetic and Logic Instructions Memory Access Instructions Control of Sequence Instructions Solution: Use Incremental Design Methodology Difficult to address all the 3 instruction type details and specificities at the same time Start with a Datapath that can execute Arithmetic and Logic Instructions Alone

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 9 COE 308 A/L Instruction Properties The processor executes the Arithmetic and Logic Instructions as follows: –Fetch the instruction from Memory –Fetch its operands. Operands are either Both registers: R-type One operand is a register and the other is an immediate value –Execute the required operation (add, sub, and, or, slt) –Store the result in the destination register

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 10 COE 308 Fetching Instructions The processor fetches the instructions from memory one by one before executing them The address is usually kept in a register called PC (Program Counter) The processor needs to know the address of the instruction to be able to fetch it The PC is the first State Element The PC is incremented to point to the next instruction in memory

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 11 COE 308 PC Block –Non-clocked memory (treated as a combinational circuit) satisfies the single cycle execution requirement The PC contains the address of the next instruction to be executed. For simplicity, we assume that the instruction and data memories are separate entities. The instruction address (PC register output) is fed into the memory to fetch the instruction from the instruction memory Question: Is the instruction memory a combinational or sequential block? –Clocked memory (synchronous) requires min. two clock cycles: 1 st to read the instruction from the memory and 2 nd to execute the instruction. Conflict with single cycle execution requirement PC Addr Instruction Ck R/Wb Dout Din Instruction Memory is read only. No need for R/Wb signal and Din bus. Iout Instructions are in memory Memory

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 12 COE 308 Register File MIPS contains 32 registers. Need a Register File First support A/L Instructions of R-type. Need 2 Read and 1 Write operation per instruction –Option 1: 1 Read/Write Port. Cannot perform 2 reads and 1 write in a single clock cycle –Option 2: 1 Read Port and 1 Read/Write Port. Cannot perform 1 read and 1 write during one clock cycle –Option 3: 2 Read Ports and 1 Write Port. Read ports are asynchronous and Write port is clocked Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Register File Coming From Instruction

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 13 COE 308 Instruction Register ? Do we need an Instruction Register to save the Fetched Instruction? No, because: Instruction Memory is asynchronous AND Single-cycle execution datapath AND PC is modified after the current instruction execution is finished PC Ck Iout PC out Delay Instruction Memory Delay No Instruction Register means: Use Output of Instruction Memory as Instruction Register

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 14 COE 308 Connecting the Register File R-type instruction format PC Addr Instruction Iout Memory opfunctrsrtrdshamt For R-type A/L instructions, connect the Rs, Rt and Rd fields of the instruction to the register address input of the register file. Bits: Connect Rs Field to Read Port Address 1 Connect Rt Field to Read Port Address 2 Connect Rd Field toWrite Port Address Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Register File Rs: I[25:21] Rt: I[20:16] Rd: I[15:11]

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 15 COE 308 Executing The Operation Use the ALU to perform the Operation. Read Register 1 Data is connected to 1 st ALU operand Zero ALUOp ALU Read Register 2 Data is connected to 2 nd ALU operand Result is written back in the Register File through the unique Write Port Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Register File Coming From Instruction RegWrite

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 16 COE 308 Getting to The Next Instruction To get to the next instruction we need to: Increment PC: PC  PC + 4 (Addressing space is in bytes, so to get to the next 32 bits which are 4 bytes, add the value 4) Wait for the rising edge of the clock Because we are in a single-cycle execution model, the PC is updated only at the rising edge of the clock which means: We should prepare the next value of the PC beforehand. We Need an adder to perform PC + 4. We have two choices: Use the ALU: Add an adder specially dedicated to adding 4 to the PC.

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 17 COE 308 Using the ALU to Increment the PC ALU Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Register File 4 PC First Option, connect the two sources PC and Registers directly to the ALU Bus Conflict

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 18 COE 308 Using the ALU to Increment the PC (2) ALU Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Register File 4 PC Second Option, connect the two sources PC and Registers through Muxes to select which block uses the ALU Need 2 phases (clock cycles)

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 19 COE 308 PC Increment Block PC + 4 No choice but to add an adder dedicated for Computing the value: PC + 4

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 20 COE 308 Datapath for R-type A/L Inst. PC + 4 Addr Instruction Iout Memory Zero ALU Read Register 1 Read Register 2 Write Register Write Data Read Data 1 Read Data 2 Register Write Register File RegWrite ALUOp

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 21 COE 308 Support for I-type Instructions For I-type Instructions, the second operand is an immediate value I-type instruction format oprsrdI Field Bits: Second Operand is a signed 16-bits immediate value: Needs to be extended to 32 bits  Sign extend it –Add Sign Extension Block The register destination number comes from the rt field (bits [20:16]) instead of coming from the rd field (bits [15:11]) –Add a Mux to select between the rd and rt field for the register destination number

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 22 COE 308 I-type Support Addr Iout Instruction Memory Zero ALU Read Reg. 1 Read Reg. 2 Write Reg. Write Data Read Data 1 Read Data 2 Register Write Reg. File Reg. Write Sign Extend Rs: I[25:21] Rt: I[20:16] Rd: I[15:11] I Field: I[15:0] Sign Extension Block added to sign extend the Immediate value from 16 to 32 bits ALU Source Mux added to select the second operand between Rs Register and The Sign Extended Immediate Value Register Destination Mux added to select the register destination number between the Rd field (R- type) and the Rt field (I-type)

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 23 COE 308 Memory Access Instructions Two instructions to access the memory: lw and sw. Both instructions use the displacement addressing mode where the address is the result of the addition of a register value to a signed displacement:EA = Rs + disp Rs is read from the Register File. So the Address Calculation takes place into the ALU. The Address is then used to access the data memory The Data Memory is a Read/Write Memory. Addr Dout Data Memory Din Two Control Signals are required for the Data Memory: MemRead and MemWrite MemRead MemWrite

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 24 COE 308 Load Instruction Lw reads a word from the memory and stores it in the Register File The Data Memory Read Access is the same as the Instruction Memory Access. It is Asynchronous and behaves like a Combinational Circuit. The Memory Read Data need to be stored in the Register File. However, Register File Write Data input already connected to output of ALU (for Arithmetic/Logic Instructions) Solution: Insert a Mux to select between ALU output and Data memory Read Data. ALU Read Reg. 1 Read Reg. 2 Write Reg. Write Data Read Data 1 Read Data 2 Reg. File Sign Extend Addr Dout Data Memory Din Addr Iout Instruction Memory

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 25 COE 308 Store Instruction Sw writes a register into the memory Need to Connect the Din Bus of the Data Memory to the Appropriate signal Addr Iout Instruction Memory ALU Read Reg. 1 Read Reg. 2 Write Reg. Write Data Read Data 1 Read Data 2 Reg. File Sign Extend Addr Dout Data Memory Din

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 26 COE 308 Branch Equal (beq) Instruction Beq rs, rt, label:Branch to “label” if rs == rt. Means:if rs == rt  PC  PC + Offset + 4 elsePC  PC + 4 Structural Conflict: Need to 1.Compare Rs and Rt 2.Compute PC + Offset + 4 Use the ALU to perform the comparison. Add a new adder for the displacement. How to Connect 16-bit Offset to a 32-bit adder? Beq is I-type. Offset field is 16-bits signed  Sign extend it Represents a word Offset  Shift left by 2 positions In Summary  Add New Adder to Compute PC + Offset Offset is sign-extended left shifted to be 32 bits ALU is used for comparison

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 27 COE 308 Branch Equal Instruction (2) ALU Read Reg. 1 Read Reg. 2 Write Reg. Write Data Read Data 1 Read Data 2 Reg. File Sign Extend Addr Dout Data Memory Din Left Shift PC 4 ++ Mux inserted to select between: PC + Offset + 4: When it is a branch instruction and the branch is taken PC + 4: in all the other cases Addr Iout Instruction Memory

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 28 COE 308 RegDst Showing The Control Signals ALU Read Reg. 1 Read Reg. 2 Write Reg. Write Data Read Data 1 Read Data 2 Reg. File Sign Extend Addr Dout Data Memory Din Left Shift PC 4 ++ Addr Iout Instruction Memory ALUOp RegWrite ALUSrcMemtoRegMemRead MemWrite PCSrc Zero

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 29 COE 308 Control Signals SignalWidth (bits)ValueEffect PCSrc1 0Select PC + 4 1Select PC + Offset + 4 RegDst1 0Register Destination Number is taken from Rd field (bits [15:11]) 1Register Destination Number is taken from Rt field (bits [20:16]) ALUSrc1 0ALU Second Operand is Register 1ALU Second Operand is Immediate Value ALUOp3 000Add 001Sub 010And 011Or 100Slt MemtoReg1 0Select the Output of the ALU to be written in the Register File 1Select the Read Data from Memory to be written in the Register File RegWrite1 1Enables a Write to the Destination Register’s location MemWrite1 1Initiate a Write to Data Memory MemRead1 1Initiate a Read to Data Memory

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 30 COE 308 A Word about ALU Control ALU Control, as designed in section 4 has two control signals: Operation Binvert The ALU in all what preceded includes its own control signals generation block that takes the ALUOp control signal and translates it into the Operation and Binvert signals. ALU ALUOp ALU Ctrl Gen. OperationBinvert

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 31 COE 308 Control Signals Settings InstructionTypeRegDstALUSrcALUOpPCSrcMemtoRegRegWriteMemRdMemWr Add R I Sub R I And R I Or R I SltR LwI SwIX10000X001 BeqIX00011(*)X000 (*) if Zero (from ALU) is equal to 1

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 32 COE 308 Datapath and Control RegDst ALU Read Reg. 1 Read Reg. 2 Write Reg. Write Data Read Data 1 Read Data 2 Reg. File Sign Extend Addr Dout Data Memory Din Left Shift PC 4 ++ Addr Iout Instruction Memory ALUOp RegWrite ALUSrcMemtoRegMemRead MemWrite PCSrc Zero Control Branch RegDst RegWrite ALUSrc ALUOp MemtoReg MemRead MemWrite Branch

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 33 COE 308 Multicycle Implementation Multiple clock cycles to execute a single instruction Clock cycle is shorter No conflict between different operations on block usage. A block can be used by an entity in a clock cycle and reused to do something else in another clock cycle Need intermediate registers to save intermediate values Optimal implementation: shortest clock cycle time.vs. smallest number of clock cycles per instruction

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 34 COE 308 How many clock cycles ? Choose a clock cycle to perform ONE operation at a time. For example: –Instruction Fetch –Operand Fetch –ALU Operation –PC  PC + 4 –Memory Access –Result Write Back in Register File

King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department College of Computer Science And Engineering College of Computer Science And Engineering Datapath Design 35 COE 308 Instruction Fetch PC  Instruction Memory Read Instruction Store Instruction into Instruction Register PC Addr Iout Instruction Memory IR IR Introduced to allow PC to change its value without waiting until the last clock cycle of the instruction execution Since ALU is unused during the Instruction Fetch cycle: Use the ALU to perform PC + 4 and store it back in the PC 4