Jianchun Wang Syracuse University 10/16/99 CLEO Meeting Outline DAQ problems solved Recent results Status of DAQ Work to be done

10/16/99 Jianchun WANG, Syracuse University 2 DAQ Problems Solved  Software problem  Corrupted data  DAQ bug, results in digital +2 V not set  Hardware problems in digital data boards  VME buffer/driver destroyed ( 14 boards affected )  Wrong VME and Sequencer code  ADC buffer damaged ( 20 boards affected )  Buffer enable conflict  Timing problem  Wrong timing caused wrong ADC to be read out

10/16/99 Jianchun WANG, Syracuse University 3 Corrupted Data o Noise expected to be 3-4 ADC counts (~500 e) o DAC address 0-3 was shifted to be 1-4 o Effectively digital +2V not set o Bug fixed and noise as good as expected o Parameter monitor and alarm working now Pedestal RMS (ADC counts)

10/16/99 Jianchun WANG, Syracuse University 4 Noise Performance Each crate checked, no problem with CC and cable Half cylinder tested simultaneously with repaired boards Total noise ~ 3.6 ADC counts Incoherent noise ~ 2.6 ADC counts (400 e)

10/16/99 Jianchun WANG, Syracuse University 5 Parameter Monitor ****************************** * Crate: 123 Board: 4 * * Board ID: RICH ANALOG A025 * ****************************** ** Board values** Ch. 0 -> +5 analog: V Ch. 1 -> -5 analog: V Ch. 2 -> +2 digital: V Ch. 3 -> -2 digital: V Ch. 4 -> board temp: C Ch. 5 -> cal pulse: V ** Cell values** Ch. 0 -> +2 analog: V Ch. 1 -> -2 analog: V Ch. 2 -> Vfp: V Ch. 3 -> Vfs: V Ch. 4 -> Vref: V Ch. 5 -> prebias: mA Ch. 6 -> shabias: mA Ch. 7 -> iBuf: mA Ch. 8 -> thermistor: C Ch. 9 -> ADC offset: V  Parameter monitor: Voltages, Bias currents, Temperatures  protect data board, chamber, ensure data quality  Readout via SBUS  By Bayar & Jian  Auto measurement and alarm implemented  Need to integrate into main slow control and alarm system

10/16/99 Jianchun WANG, Syracuse University 6 Data Boards

10/16/99 Jianchun WANG, Syracuse University 7 ADC Buffer Problem  ADC readout difference is small within one chain with no front end electronics connected  Difference of 256 suggests that bit 8 may be wrong  Buffer damaged and bits shorted  Wrong buffer enable before initialization and during reprogramming  All 20 boards repaired ; all digital boards modified pull-up resistor array

10/16/99 Jianchun WANG, Syracuse University 8 Timing Problem o Wrong buffer timing or FIFO timing may cause wrong ADC selected (duplication, rotation ) o Test chain with no CC4 used to check all boards o 4 boards found such problem o All boards are adjusted

10/16/99 Jianchun WANG, Syracuse University 9 Wirepulse Calibration Calibration pulse sent to anode wire and measure induced charge Half cylinder shown here Signal height quite uniform Dead channels 0.4%

10/16/99 Jianchun WANG, Syracuse University 10 Plane Radiator

10/16/99 Jianchun WANG, Syracuse University 11

10/16/99 Jianchun WANG, Syracuse University 12 Status of DAQ  DAQ version 9902 and 9904 were used in the runs shown  Version 9902 uses only software trigger on TIM, so two crates can not be triggered simultaneously  Version 9904 use DFC and GCAL send trigger to TIM, configuration manager not function  DAQ version dlib (Y2K) has a successful run on two RICH crates. More functions need to be tested.  More details, see Todd’s talk

10/16/99 Jianchun WANG, Syracuse University 13 Work To Be Done  Read out all RICH crates with new DAQ system  Measure pedestal, noise performance and wirepulse calibration to find any remaining problematic boards  Test new DAQ functions including single channel calibration and data sparsification  Continue coding on online monitor  Determine the mode for big calibration  Cosmic ray run