Matlab as a Design Environment for Wireless ASIC Design June 16, 2005 Erik Lindskog Beceem Communications, Inc.

Introduction to Beceem Wireless communication system developer Using Matlab for ASIC design Product development phase: Algorithm development - Matlab Algorithm and system modeling - Matlab RTL design – Verilog RTL verification - SystemC, Verilog and Matlab SW design – C++ SW verification – C++ and Matlab

Advantages With Matlab Rich support for mathematical operations and visualization Most common tool for signal processing research Graduates in communication and signal processing engineering are typically highly familiar with Matlab Fewer people have experience in programming in C++ Full fledged programming as well as scripting language Interpretating language – Integrates well with other programs Powerful debugging support Not a typed language - Highly ‘moldable’

Matlab Simulator Design Common simulator for:  PHY algorithm development and studies  Small network full PHY studies of Effect of co- and adjacent channel interference on PHY algorithms Synchronization and hand-over Link-adaptation  Fixed point modeling  RTL signal processing reference Standalone code for  Independent lower complexity studies  Generation of independent references

Matlab Simulator Design, cont. Organization  Common core source code  Simulation examples driving source code  Single file with default parameter settings enables developers to work reasonably independently while using the common code

Open Source/Freeware Software CVS - Concurrent Version Control system Cygwin – Unix emulator for Windows CVS Tortoise – File browser based CVS client  Integrates external free software tools like ExamDiff for CVS diffing WinCVS – GUI based CVS client

Signal Processing Design Flow Module design  In standalone code, or  Direct in main simulator Floating point system modeling  Integration of modules into main simulator  Floating point performance simulations

Signal Processing Design Flow, cont. Fixed point module design  In module design environment to excite corner cases  Integrated in main simulator to get realistic signal levels Fixed point system modeling  Full system fixed performance simulations  Ability to turn fixed point on/off per block  Analysis of quantization statistics to pin-point problems

Matlab – RTL Design Flow Matlab fixed point design handed over to RTL Module verification  File-in-file-out test vector comparison between MATLAB and Verilog  Extensive testing to cover corner cases in fixed point arithmetic  Random signals to guarantee fixed point equivalence

Matlab – RTL Design Flow System testing  Side-by-side testing of Verilog and MATLAB in SystemC testbench  MATLAB simulator compiled and linked to C-program called from SystemC testbench  Verilog code excited from SystemC testbench  Verilog simulation speed is the limiting factor Common test for Matlab and Verilog code  Directed testing for initial coverage  Random testing for extensive coverage All system tests part of Matlab automated regression testing

Matlab – SW Design Flow Matlab fixed point design handed over to SW Module verification  File-in-file-out test vector comparison between MATLAB and C++ SW code  Simulation example test cases in Matlab for C++ SW code System testing  Side-by-side testing of SW on FPGA and Matlab system simulation

Fixed Point Modeling Currently performed in regular Matlab Regular arithmetic operations where precision is allowed to grow Quantization with quantization functions where precision is to be limited Automatic fixed point statistics collection

Object Oriented Fixed Point Modeling Simultaneous floating and fixed point Fixed point format embedded in variable Matlab object oriented support limited  Assignment operator cannot be overloaded – Traditional quantization with assignment operation in C++ cannot be done  Function overloading only sensitive to first argument Catalytic have an object oriented fixed point modeling tool Matlab also now have an object oriented fixed point toolbox

Fixed Point Analysis Analysis of fixed point quantization statistics  Headroom – E.g. headroom above 67 th percentile  Signal to quantization noise ratio – SQNR  Over- and underflow ratios  Signal level histogram Full system simulation fixed point analysis Example Matlab implementation  Fixed point analysis function  Example call: fxp_stat(x, 2, 5)  Store statistics in function call stack tree structure  Analyze statistics after completed simulation Block-swapping analysis  Switching of fixed and floating point blocks

Lab use of Matlab Simulator Modeling of Tx or Rx part of modem against HW Rx or Tx modem Interoperability testing with signal generators and signal analyzers MAC-PHY interoperability testing Simple RF testing Over the air transmission demonstration when combined with RF

Matlab Regression Testing Developer regression testing  To many tests to run all  Directed and/or randomly selected set of tests. Automated Regression Testing  All regression tests checked for each block of commits  Breaking commit identified for each failing regression test  Result of testing automatically ed to developer  High SNR Tx-Rx tests  Single SNR BER tests  Simulation example execution tests  RTL verification tests mimicing exact use in RTL test bench

Matlab Regression Testing, cont. Automated Random Testing  Script generating random traffic for testing of Matlab simulator and RTL  Periodic random testing of code in repository with random Tx-Rx tests  Result automatically ed to developers  Provides extensive coverage Scripting language - Matlab

Speeding up Matlab Code Scalar loops  Loop over scalar operation are slow Vectorization  Convert scalar loops to matrix operations Conversion to C-code Compilation of Matlab  Removes the need for other language  Limits the need for vectorization of code  Limits duplication of code in Matlab and C  Example compiler: Catalytic Matlab Compiler

Summary Matlab Powerful tool for signal processing design Lessens ‘distance’ between algorithms and HW Facilitates for algorithm designers to be closely involved in fixed point testing and RTL verification Interacts easily with other programs and equipment Attractive design environment for ASIC design