Memory RAM Mano and Kime Sections 6-2, 6-3, 6-4. RAM - Random-Access Memory Byte - 8 bits Word - Usually in multiples of 8 K Address lines can reference.

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Memory RAM Mano and Kime Sections 6-2, 6-3, 6-4

RAM - Random-Access Memory Byte - 8 bits Word - Usually in multiples of 8 K Address lines can reference 2 k memory locations b 1 b 2 b 3 b 4 … b n n-bit words

We call this a 1024 x 16 memory memory locations ( ) that will each hold 16-bit words.

32K x 8 Static RAM GND Vcc A12 A0 D0 D1 D2 A1 A2 A3 A4 A5 A6 A7 D7 D6 D5 D4 D3 A10 A9 A8 A S CE __ A14 OE __ A13 WE __

Static RAM A Static RAM cell - 1 bit Recall... When Select is 0, S = 0, R = 0 S-R Latch is in No Change State Outputs C and /C are both 0 Data In Complement of Data In When Select is 1, the Data in and its complement get latched into the memory cell

A PARTICULAR BIT IN A SELECTED WORD x 8 RAM 4 memory locations, 8 - bits each Bits are written in parallel

A 16 x 1 RAM Chip 16 memory locations, 1 bit each 2 k locations with k select lines 2 k =16, k = 4

Decoder controls Address Selecting Address decoder enables the RAM cell for the 1-bit word selected and disables all others Tri - State Buffer

High Impedance Tri-state buffers can be connected together to form a multiplexed output line

The inverter ensures that the enable ‘select’ bits are always complements of eachother Both buffers are enabled at the same time thus both are ‘driving’ the same line at the same time OK if values are the same (both high or both low) but if ‘opposing’ values are presented then you can expect high current resulting in SMOKE! Using a tri-state buffer for a multiplexed output

Using a 4 x 4 RAM CELL to implement a 16 x 1 RAM

Row Select Column Select

An 8 x 2 RAM using a 4 x 4 RAM CELL Array Chip Select

Dynamic RAM

1 Mbit (1,048,576) x 1 Dynamic RAM Vcc Q A0 D W Vss RASCAS A1 A2 A3 A9 A8 A7 A6 A5 A4 TF Need 20 address lines. Only have 10 address lines, A0 - A9. Multiplex lower and upper 10 address lines using RAS and CAS signals.

DRAM Bit Slice Model

Standard Symbol for a 64K x 8 RAM Chip

Remember making a 4-to-16 decoder using 5 2-to-4 decoders… En 0123 I3I3 I2I2 I1I1 I0I0 O 15 O0O0

A 256K x 8 RAM using 4 64K x 8 RAM Chips The 2 most significant bits select the RAM chip The other 16 bits address the memory locations

How about a 64K x 16 RAM using two 64K x 8 RAM chips Most significant 8 bitsLeast significant 8 bits