Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 8 - Comb. Logic 2 - Delay and Power Spring 2007

ECE 425 Spring 2007Lecture 8 - Comb. Logic 22 Announcements  Homework due Friday 2/23:  2-2, 2-5, 2-6, 2-7, 2-8, 2-9, 2-12, 2-13, 2-20  Entrance Exam due Friday 2/23  Reading  Wolf  Exam 1: Wednesday, March 7

ECE 425 Spring 2007Lecture 8 - Comb. Logic 23 Where we are...  Last Time:  Combinational Logic - Static CMOS Basic structures Electrical Characteristics  Today:  Combinational Logic - Static CMOS (cont’d) Delay Estimation Transistor Sizing Power Dissipation

ECE 425 Spring 2007Lecture 8 - Comb. Logic 24 Gate Delay  Consider an inverter with a rising input  Delay related to time to discharge / charge C L t

ECE 425 Spring 2007Lecture 8 - Comb. Logic 25 Gate Delay - Definitions V in V out t pHL 50% t pLH 50% trtr 90% 10% tftf Delay: time to reach 50% of final value t pHL (book calls this t d ) t pLH Transition Time: time between 10% and 90%: t f - fall time t r - rise time

ECE 425 Spring 2007Lecture 8 - Comb. Logic 26 N-Transistor Modes - Falling transistion  Starts in saturation; ends in linear

ECE 425 Spring 2007Lecture 8 - Comb. Logic 27 Simplifying Assumptions  Assume “Step Function” input  Model transistor as switch and resistor  Resistor approximates V ds /I d at different values of V ds  Use average of V ds /I d at: middle of linear region V lin = 0.5(V ds - V ss - V t ) maximum of saturation region V sat = (V ds - V ss )  Book calls this the “  (tau) model”

ECE 425 Spring 2007Lecture 8 - Comb. Logic 28 Modeling Transistor as Resistor  Fig 3-18, p. 128

ECE 425 Spring 2007Lecture 8 - Comb. Logic 29 Delay Calculation - Finding R n

ECE 425 Spring 2007Lecture 8 - Comb. Logic 210 Delay Calculation - Finding R n

ECE 425 Spring 2007Lecture 8 - Comb. Logic 211 Delay Calculation - Finding R p

ECE 425 Spring 2007Lecture 8 - Comb. Logic 212 Delay Calculation - Finding R p

ECE 425 Spring 2007Lecture 8 - Comb. Logic 213 Summary: Calculating R n and R p  Assume V SS =0 to simplify:

ECE 425 Spring 2007Lecture 8 - Comb. Logic 214 Example: Calculating R n  Use values from book:

ECE 425 Spring 2007Lecture 8 - Comb. Logic 215 Example: Calculating R p  Use values from book:

ECE 425 Spring 2007Lecture 8 - Comb. Logic 216 Summary: R n and R p for Minimum-Sized Transistors typeV DD =5VV DD =3.3V RnRn 3.9KΩ6.8KΩ RpRp 14KΩ25KΩ Table 3-1, p. 130

ECE 425 Spring 2007Lecture 8 - Comb. Logic 217 Inverter Delay with the  model Rising Input / Falling Output

ECE 425 Spring 2007Lecture 8 - Comb. Logic 218 Inverter Delay with the  model Falling Input / Rising Output

ECE 425 Spring 2007Lecture 8 - Comb. Logic 219 NAND Gate Delay with the  Model  Fall time: n-transistors in series t f = 2.2(2*R n +R L )C L  Rise time: 1 p-transistor on (for worst case) t r = 2.2(R p +R L )C L

ECE 425 Spring 2007Lecture 8 - Comb. Logic 220 NOR Gate Delay with the  Model  Fall time: one n-transistor on (worst case) t f = 2.2(R n +R L )C L  Rise time: p-transistor in series t r = 2.2(2* R p +R L )C L

ECE 425 Spring 2007Lecture 8 - Comb. Logic 221 AOI Gate Delay with the  Model  Fall time: 2 n-transistors in series (worst case) t f = 2.2(2*R n +R L )C L  Rise time: 3 p-transistors in series (worst case) t p = 2.2(3*R n +R L )C L

ECE 425 Spring 2007Lecture 8 - Comb. Logic 222 Delay Estimation - Other Approaches  Current source model - treat transistor as current source in saturation  Fitted model  Measure several circuit characteristics & fit to formula  Used in CAD tools  Circuit Simulation - Most accurate approach

ECE 425 Spring 2007Lecture 8 - Comb. Logic 223 Accuracy of methods  Figure 3-21, p. 134  Spice Model   Model  Current Source Model (not shown here)

ECE 425 Spring 2007Lecture 8 - Comb. Logic 224 Perspective Delay Estimation  Use simple models for  Quick prediction of delay  Insight into circuit operation  Comparison of different circuits  Later, we’ll discuss the Logical Effort delay model  Use Spice for accurate simulation

ECE 425 Spring 2007Lecture 8 - Comb. Logic 225 Example - Inverter Delay  Estimate t r and t f for a minimum-size inverter driving the inputs of four minimum-size inverters (assume loading only from transistor gates)

ECE 425 Spring 2007Lecture 8 - Comb. Logic 226 C gp = C gn = C INV = CL=CL= Example - Inverter Delay (cont’d)  Estimate loading from a single inverter:

ECE 425 Spring 2007Lecture 8 - Comb. Logic 227 tr=tr= tf=tf= t df = Example - Inverter Delay (cont’d)  Now use R n, R p, C L to calculate t r, t f t df = Average=“FO4 Delay”

ECE 425 Spring 2007Lecture 8 - Comb. Logic 228 Effect of Increased Transistor Width  Increase width of transistor to:  Increase current  Reduce effective resistance (R n or R p )  Side-effect: increased input capacitance (more about this later)

ECE 425 Spring 2007Lecture 8 - Comb. Logic 229 Transistor Sizing Example  Size the transistors in an inverter so that t r =t f  R p / R n = 13KΩ / 3.9KΩ = 3.47  Make W p approximately 3.5*W n W=3 L=2 W=10 L=2

ECE 425 Spring 2007Lecture 8 - Comb. Logic 230 Transistor Sizing Example  Size the transistors in an AOI gate so that t r =t f  R p / R n = 13KΩ / 3.9KΩ = 3.47 (“round down” to 3)  Size each worst case path for equal delay  Assume L=2 in all transistors

ECE 425 Spring 2007Lecture 8 - Comb. Logic 231 Power Consumption  Static power consumption - due to leakage current  Subthreshold current - in deep submicron devices  Total static consumption: Note influence of V t

ECE 425 Spring 2007Lecture 8 - Comb. Logic 232 Dynamic Power Consumption  Power consumed as outputs switch to  Charge load capacitances  Discharge load capacitance

ECE 425 Spring 2007Lecture 8 - Comb. Logic 233 Dynamic Power Consumption  Charging Capacitor  Current: Eq  Voltage: Eq  Energy: Eq  Discharging Capacitor: the same

ECE 425 Spring 2007Lecture 8 - Comb. Logic 234 Dynamic Power Consumption  Total energy dissipated in charge/discharge cycle:  Power consumption (energy/time) - EQ 3-17: Note: f is an activity rate, not (usually )the clock frequency

ECE 425 Spring 2007Lecture 8 - Comb. Logic 235 Power Consumption - Key Points  Power consumption depends only on C L, and V DD  What is the effect of transistor sizing?  For overall chip: Average activity rate Total on-chip capacitance

ECE 425 Spring 2007Lecture 8 - Comb. Logic 236 Power Consumption and V DD  Reducing V DD creates large reduction in P  If we reduce V DD to V DD ’,

ECE 425 Spring 2007Lecture 8 - Comb. Logic 237 Delay and V DD  Tradeoff: reducing V DD increases delay  If we reduce V DD to V DD ’,  Tradeoff: reducing V DD decreases noise immunity (more careful design necessary!)

ECE 425 Spring 2007Lecture 8 - Comb. Logic 238 Design Strategies for Power Reduction  Use lower V DD to reduce power  Compensate for higher delays by  Using newer, smaller, faster IC technology  Trading off “more slower logic” for “less faster logic” - this is called voltage scaling  Examples (from Tom Burd’s “General Processor Information”)  Intel P5 Pentium: V DD =5.0V / f clk =66MHz / P=16W  Intel P54C: V DD =3.3V / f clk =100MHz / P=5.0W  Intel P6: V DD =3.3V/ f clk =166MHz / P=23.4W  Compaq Alpha 21264: V DD =2.0V / f clk =667MHz / P=72W  Intel Pentium 4: V DD =1.4V / f clk =2.5GHz / P=55W

ECE 425 Spring 2007Lecture 8 - Comb. Logic 239 Speed-Power Product  A way of characterizing the quality of a logic family  For static complementary CMOS  Bottom line: easiest way to reduce power is to reduce V DD

ECE 425 Spring 2007Lecture 8 - Comb. Logic 240 Parasitics and Performance  Consider the following layout:  What is the impact on performance of parasitics  At point a (VDD rail)?  At point b (input)?  At Point c (output)? b a c

ECE 425 Spring 2007Lecture 8 - Comb. Logic 241 Parasitics and Performance  a - power supply connections  capacitance - no effect on delay  resistance - increases delay (see p. 135) minimize by reducing difffusion length minimize using parallel vias b a c

ECE 425 Spring 2007Lecture 8 - Comb. Logic 242 Parasitics and Performance  b - gate input  capacitance increases delay on previous stage (often transistor gates dominate)  resistance increases delay on previous stage b a c

ECE 425 Spring 2007Lecture 8 - Comb. Logic 243 Parasitics and Performance  c - gate output  resistance, capacitance increase delay  Resistance & capacitance "near" to output causes additional delay b a c

ECE 425 Spring 2007Lecture 8 - Comb. Logic 244 Driving Large Loads  Off-chip loads, long wires, etc. have high capacitance  Increasing transistor size increases driving ability (and speed), but in turn increases gate capacitance  Solution: stages of progressively larger transistors  Use n opt = ln(C big /C g ).  Scale by a factor of  =e

ECE 425 Spring 2007Lecture 8 - Comb. Logic 245 Summary: Static CMOS  Advantages  High Noise Margins (V OH =V DD, V OL =Gnd)  No static power consumption (except for leakage)  Comparable rise and fall times (with proper sizing)  Robust and easy to use  Disadvantages  Large transistor counts (2N transistors for N inputs) Larger area More parasitic loading (2 transistor gates on each input)  Pullup issues Lower driving capability of P transistors Series connections especially problematic Sizing helps, but increases loading on gate inputs

ECE 425 Spring 2007Lecture 8 - Comb. Logic 246 Alternatives to Static CMOS  Switch Logic  nmos  Pseudo-nmos  Dynamic Logic  Low-Power Gates

ECE 425 Spring 2007Lecture 8 - Comb. Logic 247 Coming Up  Switch-Based Logic using Pass Transistors  Aside: D/A Conversion  Labs 5-7: Hierarchical Layout of a DAC  Alternative Logic Families