CS Spring 2007 – Lec #18 – Mid #2 Review - 1 Understanding Engineers #1 zThe graduate with a Science degree asks, "Why does it work?" zThe graduate with an Engineering degree asks, "How does it work?" zThe graduate with an Accounting degree asks, "How much will it cost?" zThe graduate with an Arts degree asks, "Do you want fries with that?"

CS Spring 2007 – Lec #18 – Mid #2 Review - 2 Understanding Engineers #2 zMS CS -- Soft-ware zMS EE -- Hard-ware zMBA -- Un-a-ware zMFA -- No-ware

CS Spring 2007 – Lec #18 – Mid #2 Review - 3 Midterm II zTHIS Thursday, 22 March (that is TWO days from today!), 2: :30+, CS 150 Lab zLectures 10, 11, 12, (no lecture 13!), 14, 15, 16; Labs #4 and #5 (Debugging/Logic Analyzers) + Checkpoints #0 and #1 (SDRAM + Video Encoder) zDon’t forget: Spring 05/Fall 05 exams are on-line! z5 x 10 point questions, mostly design-oriented zClosed book, open crib sheet; PENCIL, not pen! zTwo review sessions: Tu 8 PM and W 8 PM in the lab zNOTE: Discussion sections and lab lecture cancelled this week

CS Spring 2007 – Lec #18 – Mid #2 Review - 4 Sequential Logic Implementation zModels for representing sequential circuits yMealy, Moore, and synchronous Mealy machines yVerilog specifications for state machines zFinite state machine design procedure yDeriving state diagram from word specifications yDeriving state transition table yDetermining next state and output functions yImplementing combinational logic

CS Spring 2007 – Lec #18 – Mid #2 Review - 5 SDRAM Memory Controller zStatic RAM Technology y6T Memory Cell yMemory Access Timing zDynamic RAM Technology y1T Memory Cell yMemory Access Timing zTheory in lecture, but practical detailed memory system organization and timing in Lab Checkpoint #0

CS Spring 2007 – Lec #18 – Mid #2 Review - 6 Two-way Video Conferencing Project zProject Concept and Background zSDRAM Controller (Checkpoint #0) zVideo Encoder/Display System (Checkpoint #1)

CS Spring 2007 – Lec #18 – Mid #2 Review - 7 Videoconferencing System Concept Display Video Encoder (Checkpoint #1) Video Decoder Camera Videostream Video Decoder Checkpoint #2 Checkpoint #4 SDRAM (Checkpoint #0) Multiport SDRAM Memory System Multiport Arbitration Wireless Transceiver (Checkpoint #3)

CS Spring 2007 – Lec #18 – Mid #2 Review - 8 Computer Organization zComputer design as an application of digital logic design procedures zComputer = processing unit + memory system zProcessing unit = control + datapath zControl = finite state machine yInputs = machine instruction, datapath conditions yOutputs = register transfer control signals, ALU operation codes yInstruction interpretation = instruction fetch, decode, execute zDatapath = functional units + registers yFunctional units = ALU, multipliers, dividers, etc. yRegisters = program counter, shifters, storage registers

CS Spring 2007 – Lec #18 – Mid #2 Review - 9 Register Transfer Ld C A Sel 0 B Sel 1 DECDEC Sel 0101 C  A Sel  0; Ld  1 C  B Sel  1; Ld  1 Clk Sel Ld Clk A on Bus Ld C from Bus Bus B on Bus ?

CS Spring 2007 – Lec #18 – Mid #2 Review - 10 Register Transfer zPoint-to-point connection yDedicated wires yMuxes on inputs of each register zCommon input from multiplexer yLoad enables for each register yControl signals for multiplexer zCommon bus with output enables yOutput enables and load enables for each register rt MUX rs MUX rd MUX R4 MUX rs MUX rtrdR4 BUS rsrtrdR4

CS Spring 2007 – Lec #18 – Mid #2 Review - 11 State Machine Implementation zAlternative controller FSM implementation approaches based on: yClassical Moore and Mealy machines yTime state: Divide and Counter yJump counters yMicroprogramming (ROM) based approaches xbranch sequencers xhorizontal microcode xvertical microcode

CS Spring 2007 – Lec #18 – Mid #2 Review - 12 Time State (Divide & Conquer) Time State FSM Most instructions follow same basic sequence Differ only in detailed execution sequence Time State FSM can be parameterized by opcode and AC states Instruction State: stored in IR Condition State: stored in AC T0 T1 T2 T3 T4 T5 T6 T7 Wait/ BRN AC  0/ (LD + ST + ADD) Wait/ BRN + (ST Wait)/ (LD + ADD) Wait 

CS Spring 2007 – Lec #18 – Mid #2 Review - 13 Jump Counters Pure Jump Counter Logic blocks implemented via discrete logic, PLAs, ROMs NOTE: No inputs to jump state logic

CS Spring 2007 – Lec #18 – Mid #2 Review - 14 Jump Counters Hybrid Jump Counter Load inputs are function of state and FSM inputs

CS Spring 2007 – Lec #18 – Mid #2 Review - 15 Jump Counters CLR, CNT, LD implemented via Mux Logic Active Lo outputs: hi input inverted at the output Note that CNT is active hi on counter so invert MUX inputs! CLR = CLRm + Reset

CS Spring 2007 – Lec #18 – Mid #2 Review - 16 Branch Sequencers 4 Way Branch Sequencer Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states Mux I n p u t s 64 Word ROM   state x11 x10 x01 x00 Z Y X W C o n t r o l S i g n a l s a0 a1 a2 a3 a4 a5 N WX Y Z 

CS Spring 2007 – Lec #18 – Mid #2 Review - 17 Branch Sequencers Alternative Horizontal Implementation Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In example FSM, input MUX can be 2:1! Adding length to ROM word saves on bits vs. doubling words Vertical format: (14 + 4) x 64 = 1152 ROM bits Horizontal format: ( x 4 + 2) x 16 = 512 ROM bits

CS Spring 2007 – Lec #18 – Mid #2 Review - 18 Vertical Microprogramming Branch Jump Compare indicated signal to 0 or 1 Register Transfer Source, Destination, Operation 10 ROM Bits

CS Spring 2007 – Lec #18 – Mid #2 Review - 19 Vertical Programming Controller Block Diagram

CS Spring 2007 – Lec #18 – Mid #2 Review - 20 Design/Reverse Engineering zDesign Procedure: Specification --> Abstract Design --> Concrete Implementation yE.g., “What the state machine is supposed to do” to state diagram to jump counter implementation zReverse Engineering: Concrete Implementation --> Abstract Design --> Specification yE.g., Jump counter implementation to state diagram to “what the state machine is supposed to do”