November-2007Created By: Matt Heath MicroNet Digital Core Design ECE – 401 Senior Design Presentation

November-2007Created By: Matt Heath MicroNet Digital Core - Team Team Members: – CSU Student(s) Matt Heath – Digital Core Circuit (Hardware) – Woodward Member(s) Clayton Rehbien – Project Sponsor Pat McKeon – Project Manager Tena Britt – Mentor Rollins Linser – I/O Circuits (Hardware) Dennis Belt – Lead Engineer Dave Peterson – Software Engineer Bill Becker - Marketing Nancee Ault – Designer

November-2007Created By: Matt Heath MicroNet Digital Core - Introduction

November-2007Created By: Matt Heath MicroNet Digital Core – Overview Reason for the Project – Current modules are facing parts obsolescence. Intel 196 Family Motorola DSP5600 Family –Discrete I/O Circuit Design – Circuit and Layout re-use for all modules – Reduce circuit real estate on current modules

November-2007Created By: Matt Heath MicroNet Digital Core – Current Goals Goals / Deliverables: – Complete Detailed Requirements – Start Digital Core Circuit Schematic Board Layout

November-2007Created By: Matt Heath MicroNet Digital Core – Application Interface with the VME Bus – 32 bit data bus – 24 bit address bus – Other command signals Interface with the I/O circuits – Discrete or Analog circuits Health Monitoring Other Specific Functions for Individual Modules

November-2007Created By: Matt Heath MicroNet Digital Core – Design Design is based on: – Marketing Requirements Has to be backwards compatible Has to support future architecture – Other issues with current module Looked at past repair reports Researched the Woodward knowledgebase articles

November-2007Created By: Matt Heath MicroNet Digital Core – Design Microprocessor Selection

November-2007Created By: Matt Heath MicroNet Digital Core – Design Microprocessor Selection (continued)

November-2007Created By: Matt Heath MicroNet Digital Core – Design FPGA Design – Pin Count I/O pins Data and address pins Signal pins (VME bus & module CPU interface) – Gate Amount Received an approximate amount from Software Engineers

November-2007Created By: Matt Heath MicroNet Digital Core – Design Simulations – HyperLynx From Mentor Graphics

November-2007Created By: Matt Heath MicroNet Digital Core – Design Design Road blocks – Bus Voltage FPGA – 3.3V 565 – 2.6V – Sync. The FPGA with 565 Processor – Re-program the firmware when it is at the customer site. Service Pack Style of distribution

November-2007Created By: Matt Heath MicroNet Digital Core – Budget Current Costs – Engineering Labor $15,000 Note: Labor is for all people working on the project except me. – Material Xilinx Spartan-3A FPGA Engineering Board –$ Future Costs – Circuit Board $700.00/ circuit board – Engineering Labor $200,000.00

November-2007Created By: Matt Heath MicroNet Digital Core – Future Goals for Spring Semester (ECE-402) Goals/Deliverables – Digital Core Circuit Schematics – Digital Core Circuit Layout – Test Results for Circuit – Digital Core Specifications/Paperwork Circuit Analysis  HyperLynx Simulations  HyperLynx Tolerance Stack-ups  MathCAD and Excel Timing Margins  HyperLynx

November-2007Created By: Matt Heath MicroNet Digital Core – Conclusion Thank You!