Multiplexers Lecture L6.6v Section 6.2. Multiplexers A Digital Switch A 2-to-1 MUX A 4-to-1 MUX A Quad 2-to-1 MUX The Verilog if…else Statement TTL Multiplexer.

Slides:

Advertisements

Similar presentations

Verilog in transistor level using Microwind

Advertisements

CPSC 321 Computer Architecture Andreas Klappenecker

CDA 3100 Recitation Week 11.

//HDL Example 4-10 // //Gate-level description of circuit of Fig. 4-2 module analysis (A,B,C,F1,F2); input.

Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN

Supplement on Verilog adder examples

EE 361 Fall 2003University of Hawaii1 Hardware Design Tips EE 361 University of Hawaii.

Verilog Modules for Common Digital Functions

CPEN Digital System Design

Table 7.1 Verilog Operators.

Anurag Dwivedi.  Verilog- Hardware Description Language  Modules  Combinational circuits  assign statement  Control statements  Sequential circuits.

Multiplexer as a Universal Function Generator Lecture L6.7 Section 6.2.

Magnitude Comparator Lecture L6.4 Section 6.1.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

7-Segment LED Display DD: Section Mano: Section 3.10.

Decoders Discussion D9.5 Example 25. Decoders 3-to-8 Decoder decoder38.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all;

Edge-Triggered D Flip-Flops

ECE Synthesis & Verification - Lecture 0 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits VLSI.

Pulse-Width Modulated DAC

Multiplexers Lecture L6.4 Section 6.4.

CS 151 Digital Systems Design Lecture 15 Magnitude Comparators and Multiplexers.

First Steps in Verilog CPSC 321 Computer Architecture Andreas Klappenecker.

Shifter Lecture L7.4 Group HW #4 Section 10.3.

CS 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.

Multiplexers Module M6.1 Section 6.4. Multiplexers A 4-to-1 MUX TTL Multiplexer A 2-to-1 MUX.

Adders Lecture L7.1 Section 6.2 Section 10.4 (pp )

Arbitrary Waveform Discussion 12.2 Example 34. Recall Divide-by-8 Counter Use q2, q1, q0 as inputs to a combinational circuit to produce an arbitrary.

Counters Discussion 12.1 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

2-to-1 Multiplexer: if Statement Discussion D7.1 Example 4.

Decoders Module M9.1 Section 6.3. Decoders TTL Decoders.

4-to-1 Multiplexer: Module Instantiation Discussion D7.2 Example 5.

A/D Converter Datapaths Discussion D8.4. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit:

Homework Reading Machine Projects Labs

ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)

Generic Multiplexers: Parameters Discussion D7.5 Example 8.

Introduction to Verilog Multiplexers. Introduction to Verilog Verilog Hardware Description Language (Verilog HDL) released by Gateway Design Automation.

Top-level Verilog Designs Discussion D9.1 Example 12.

D Flip-Flops in Verilog Discussion 10.3 Example 27.

Quad 2-to-1 Multiplexer Discussion D7.4 Example 7.

Digital Logic Review Discussion D8.7.

7-Segment Display DIO1 Board Verilog.

Decoders and Encoders Discussion D4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

Engineering 100 Section 250 Combinational Logic -- Examples 9/13/2010.

Mantıksal Tasarım – BBM231 M. Önder Efe

Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 5.

Verilog Intro: Part 2. Procedural Blocks There are two types of procedural blocks in Verilog. – initial for single-pass behavior: initial blocks execute.

Figure 6.1. A 2-to-1 multiplexer.

Combinational Circuits

Combinational Logic By Taweesak Reungpeerakul

Lecture # 11 University of Tehran

Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL) A hardware description language is a language or means used to describe or model a digital.

Functions of Combinational Logic By Taweesak Reungpeerakul

ECE/CS 352 Digital System Fundamentals© 2001 C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapters 3 and 4: Verilog – Part 2 Charles R.

CS 151  What does the full truth table look like? InputsOutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX

 A test bench is an HDL program used for applying stimulus to an HDL design in order to test it and observe its response during simulation.  In addition.

Multiplexers Section Topics Multiplexers – Definition – Examples – Verilog Modeling.

Dual Sparkle Circuit Green connections are wires – they can be any colour. Make sure all + and - connections match up. Make sure the larger battery terminal.

CSE 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.

1 Modeling Combinational Logic Circuits Debdeep Mukhopadhyay Associate Professor Dept of Computer Science and Engineering NYU Shanghai and IIT Kharagpur.

Signed Arithmetic TYWu. Verilog 2001 Verilog 1995 provides only one signed data type, integer. Verilog 2001 provides a very rich set of new signed data.

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part4: Verilog – Part 2.

Designing Combinational Logic Circuits in Verilog - 1

Magnitude Comparator Module M5.2 Section 6.1.

The Multiplexer Multi what?

Logic Values 0:logic 0 / false 1:logic 1 / true X:unknown logic value

Logic Design Review – 2 Basic Combinational Circuits

Logic Values 0:logic 0 / false 1:logic 1 / true X:unknown logic value

Logic Values 0:logic 0 / false 1:logic 1 / true X:unknown logic value

Magnitude Comparator Lecture L6.2 Section 6.1.

Presentation transcript:

Multiplexers Lecture L6.6v Section 6.2

Multiplexers A Digital Switch A 2-to-1 MUX A 4-to-1 MUX A Quad 2-to-1 MUX The Verilog if…else Statement TTL Multiplexer

Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3

Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 0 A multiplexer is a digital switch

Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 0 1

Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 1 0

Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 1

A 2 x 1 MUX Z = A & ~s0 | B & s0

A 4 x 1 MUX A = ~s0 & C0 | s0 & C1 B = ~s0 & C2 | s0 & C3 Z = ~s1 & A | s1 & B Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3)

A 4 x 1 MUX Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3) Z = ~s1 & ~s0 & C0 | ~s1 & s0 & C1 | s1 & ~s0 & C2 | s1 & s0 & C3

Y s 0 A 1 B Problem How would you make a Quad 2-to-1 MUX? s [A3..A0] [B3..B0] [Y3..Y0] Quad 2-to-1 MUX

mux.v module mux24(A,B,s,Y); input [3:0] A; input [3:0] B; input s; output [3:0] Y; wire [3:0] Y; assign Y = {4{~s}} & A | {4{s}} & B; endmodule s [A3..A0] [B3..B0] [Y3..Y0] Quad 2-to-1 MUX

mux.v module mux24(A,B,s,Y); input [3:0] A; input [3:0] B; input s; output [3:0] Y; wire [3:0] Y; if(s == 0) Y = A; else Y = B; endmodule s [A3..A0] [B3..B0] [Y3..Y0] Quad 2-to-1 MUX

TTL Multiplexer GND Vcc1G B 1C3 1C2 1C1 1C0 1Y 2G A 2C3 2C2 2C1 2C0 2Y 74LS153 X X X X X X X X X X X X X 0 X X X 1 X X X X 0 X X X 1 X X X X X X X B A C0 C1 C2 C3 G Y Dual 4-to-1-line multiplexer