Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester

11/06/ Outline Introduction Study implementation Global interconnect optimization issues  Inductance effect  Wire sizing  Repeater insertion  Via parasitics Conclusions

11/06/ Performance Prediction Performance estimated from critical path analysis Previous prediction assumes:  RC line model for interconnect delay  Optimal repeater sizing and ideal placement  Switch factor bounded by {0,2}  Design constraints excluded, such as noise margin, delay uncertainty and area cost  Via resistance from buffer insertion neglected Critical Path Delay Estimation

11/06/ Study Implementation GSRC Technology Extrapolation (GTX) Engine as study framework Typical 0.18μm device technology and 15mm copper global interconnect, line thickness=1.3μm

11/06/ Inductance Effect on Line Delay Line behavior is RLC dominant when b b 2 <0, where b 1 =R s C+R s C L +RC L, b 2 =R s C 2 /6+R s RCC L /2+RC 2 /24+R 2 CC L /6+LC+LC L Interconnect Length (mm) Interconnect Delay (ps) RC_Bakoglu RLC_Friedman RLC_Kahng/Muddu HSPICE LC-dominated Case

11/06/ Shielding Technology Shielding is helpful to define the current return path for inductance coupling and to reduce crosstalk noise Cost = Signal wire pitch x Repeater sizing factor x Number of repeaters No Shielding (NS) One Side Shielding (1S) Two Side Shielding (1S) Vdd/GND Lines Signal Lines

11/06/ Shielding Cost Optimization Variables for cost optimization: repeater size, number of repeaters, wire width and spacing Cost Optimization Constrains: Line Delay < 1ns; Noise peak < 20% V dd ; Transition time < 500ps; Delay uncertainty (?) Ignoring inductance can overestimate chip cost (>20%) Optimized Cost within Constraints RC/SF=1 RC/SF=2 RC/SF=3 RLC/SF=1 RLC/SF=2 RLC/SF=3 NS 1S 2S

11/06/ Wire Size Optimization Formula: W opt (l)=[R in (C f l+2C L )/(2R D C a )] 1/2 * Formula has up to 30% error from RLC model *J. Cong and D.Z. Pan, “Interconnect Estimation and Planning for Deep Submicron Designs”, Proc. DAC, 1999, pp Repeater size = 100 X min Repeater size = 50 X min Formula RC, 1 pole RLC Optimal Wire Width (μm) Line Length (mm)

11/06/ Repeater Size Optimization Bakoglu sizing: S=[R D C int /(R int C in )] 1/2 Simple sizing expression overestimates optimal repeater size

11/06/ Repeater Placement Uncertainty Repeater placement uncertainty ε has a large impact on peak noise (up to >70%) but little impact on delay (<5%) L seg ε·L seg

11/06/ Staggered Insertion of Repeaters Normal (non-staggered) Repeater Insertion Staggered Repeater Insertion Staggered insertion significantly reduces peak noise and almost eliminates delay uncertainty* *A. B. Kahng, S. Muddu, and E. Sato, “Tuning Strategies for Global Interconnects in High-Performance Deep Submicron IC’s”, VLSI Design 10(1), 1999, pp

11/06/ Via Parasitics Via resistance is 47Ω/via for 0.18μm technology (signal line resistance is about 20Ω/mm) Ignoring via parasitic resistance can introduce 10-20% underestimation of delay In the future: more metal levels will causes larger via resistance; but copper technology can significantly reduce it

11/06/ Conclusions Analytical models need to be carefully applied on line delay and noise estimation Conventional models may lead to large error in optimal sizing Realistic conditions (layout uncertainty, via parasitics, shielding case, etc.) are important for correct prediction GTX can be a powerful tool for quantified prediction