Camera Auto Focus Presentation 6, February 28 th, 2007 Team W1: Tom Goff (W11) David Hwang (W12) Kate Killfoile (W13) Greg Look (W14) Design Manager: Bowei Gai Project Goal: Design a low-power, small auto focus chip for a camera or other hand-held device

Status Last Time –Exhaustive simulations –Schematic This Week Rigorous schematic testing Control logic structural Verilog Sub-module layout In Process… Layout Schematic of control logic Unfinished Extraction, LVS, post-layout simulation

Design Decisions Split up FSM logic (detailed later) Decided on an adder Settled on sense amp registers Crazy optimizations of schematic

Updated Transistor Count ComponentFull Chip Count AG Preprocessor2,274 Delta I Preprocessor2,624 FP multiplier5,832 FP adder994 Power control~1,000 Buffers2,000 Total~17,182 Still fluctuating…

Control Logic FSM’s

Compare [1:0] Enable Global rst FSM 1 Next State Logic Pulse Generator Next state Output Logic Reg[1]Reg[0] Enable next FSM Reset Clock

Compare [3:2] Enable FSM 1 Global rst FSM 2 More complicated next state logic Pulse Generator Next state [2:0] Output Logic Reg[3]Reg[2] Mux Lines [6:0] Reset Clock

Bus Widths Counter[?:0] Compare 0 Compare 1 FSM 1 FSM 2 Global rst Clk Reset Line Enable FSM 2 Bus PathBits To FSM 1 3 To FSM 2 2 To Counter1

Schematic Verification Every module completely tested Excluding power logic

Layout Progress ModulesLayout Completed Basic gates100% Registers100% Muxes100% Adders25% Shifters0% Integer multiplier0%

Full Adder

Registers

Muxes

Next Steps Sleep briefly Continue laying out modules Complete control logic schematic

Problems Pass transistors make for terrible layouts Shared libraries are a pain Selfish cluster users crowding our space; many deaths Difficult to synchronize FSM’s

Questions

References None this week