S. RossEECS 40 Spring 2003 Lecture 24 Today we will Review charging of output capacitance (origin of gate delay) Calculate output capacitance Discuss fan-out Discuss “complementary” nature of CMOS Lecture 24

S. RossEECS 40 Spring 2003 Lecture 24 A F B S S S S PMOS 1 NMOS 1 PMOS 2 NMOS 2 V DD ORIGIN OF GATE DELAY This is GATE DELAY. When the inputs A and B change such that the output F changes, the output cannot change instantaneously; the output capacitance must be charged or discharged.

S. RossEECS 40 Spring 2003 Lecture 24 In our logic circuits, the NMOS transistors have REVIEW: PULL-DOWN DEVICES Gate terminal connected to V IN Source terminal connected to ground directly, or through another NMOS This means When V IN is high, NMOS transistors are “on”. They help pull-down V OUT to ground, by conducting current to discharge the output capacitance. When V IN is low, NMOS transistors are “off”. They act as open circuits from source to drain.

S. RossEECS 40 Spring 2003 Lecture 24 In our logic circuits, the PMOS transistors have REVIEW: PULL-UP DEVICES Gate terminal connected to V IN Source terminal connected to V DD directly, or through another PMOS This means When V IN is low, PMOS transistors are “on”. They help pull-up V OUT to V DD, by conducting current to charge the output capacitance. When V IN is high, PMOS transistors are “off”. They act as open circuits from source to drain.

S. RossEECS 40 Spring 2003 Lecture 24 There is a model for the behavior of transistors in a CMOS logic circuit to analyze charging/discharging of the output capacitance. D G S V IN = V DD (for NMOS) V IN = 0 (for PMOS) D G S REVIEW: MODEL FOR GATE DELAY ANALYSIS R R V IN = 0 (for NMOS) V IN = V DD (for PMOS) The resistance R is the effective resistance for the device during the first half of the transition. Each device can have different R!

S. RossEECS 40 Spring 2003 Lecture 24 REVIEW: CALCULATING EFFECTIVE RESISTANCE V DS(N) I D(N) V DD V DD /2 t=0 I D(N) ≈ I DSAT(N) t=t p I D(N) ≈ I DSAT(N) V OUT V DD Consider pull-down, when V OUT must go from V DD to 0 V. RNRN RPRP We calculate R N by averaging the values of V DS(N) /I D(N) at the beginning and ending of delay. R N = ¾ V DD / I DSAT(N) R P = -¾ V DD / I DSAT(P)

S. RossEECS 40 Spring 2003 Lecture 24 CALCULATING OUTPUT CAPACITANCE Two major sources of capacitance: 1.The transistor gates in the next stage 2.The metal connection to the next stage Both can be computed using the parallel plate capacitor formula: A is the area of the plates, k is the dielectric constant of the insulator in between the plates, e 0 is the permittivity of free space, and d is the distance in between the plates. We denote since this is fixed by fabrication process.

S. RossEECS 40 Spring 2003 Lecture 24 Each transistor gate terminal attached to the output contributes a gate capacitance where W and L are the channel dimensions and C OX is the capacitance of the gate per unit area (parameters from I D vs. V DS ). Each metal connection at the output contributes a capacitance also given by the parallel plate capacitor formula, but with different length, width, and capacitance per unit area. CALCULATING OUTPUT CAPACITANCE

S. RossEECS 40 Spring 2003 Lecture 24 EXAMPLE S V DD S V OUT1 V OUT2 S S S S V DD V IN Suppose that V IN was logic 1 for a long time, and then switches to logic 0 at t = 0. Find the propagation delay through the inverter.

S. RossEECS 40 Spring 2003 Lecture 24 Use V DD = 5 V V TH(N) = -V TH(P) = 1 V C OX = 5 fF/µm 2 for both transistors L = 2 µm for both transistors W = 2 µm for both transistors  = 0 for both transistors µ N = mm 2 / (V s) µ P = mm 2 / (V s) W I = 2 µm L I = 200 µm C OX(I) = 0.1 fF/µm 2 EXAMPLE Calculate the effective resistance and total output capacitance due to gate and interconnect capacitance.

S. RossEECS 40 Spring 2003 Lecture 24 EXAMPLE Since V IN is now low, V OUT1 must go from low to high. Pull-up S S V IN = 0 V V DD V OUT V DD RNRN RPRP R P is the resistance involved in the charging.

S. RossEECS 40 Spring 2003 Lecture 24 EXAMPLE R P = - ¾ V DD / I DSAT(P) R P = - ¾ (5 V) / (W/L  P C OX (V GS(P) – V TH(P) ) 2 ) R P = - ¾ (5 V) / (2  m/2  m mm 2 /Vs 5 fF/  m 2 (-5 V – -1V) 2 ) R P = k  Now calculate C OUT : There are 4 transistor gates attached to inverter output, and one wire connecting the inverter output to the NAND input. C OUT = 4 C G + C I

S. RossEECS 40 Spring 2003 Lecture 24 EXAMPLE C G = W L C OX = (2  m)(2  m)(5 fF/  m 2 ) = 20 fF C I = W I L I C OX(I) = (2  m)(200  m)(0.1 fF/  m 2 ) = 40 fF C OUT = 4 C G + C I = (4)20 fF + 40 fF = 100 fF t P = 0.69 R P C OUT = 0.69 (1.875 k  ) (100 fF) = 129 ps

S. RossEECS 40 Spring 2003 Lecture 24 FAN-OUT Consider our previous example. Suppose that we connected N NAND gates to the output of the inverter. Each NAND gate adds 4 more gate capacitances and another interconnect capacitance. C OUT = N(4 C G + C I ) = 100 N fF t p = 129 N ps The fan-out, or number of logic gates that can be attached to an output, is limited by propagation delay considerations.

S. RossEECS 40 Spring 2003 Lecture 24 LOOKING AT CMOS CIRCUITS A B C A B C V DD F One can often “see” the logical operation in a CMOS circuit by looking at either the top or bottom half of the circuit. For example, looking at the top half of this circuit, we see that the output will be connected to V DD (F is high) when: (B OR C is low) AND A is low F = (B + C) A

S. RossEECS 40 Spring 2003 Lecture 24 LOOKING AT CMOS CIRCUITS A B C A B C V DD F The bottom half of the circuit always results in the same equation as the top half, just rewritten via DeMorgan (that’s why output is always defined). Looking at the bottom half of this circuit, we see that the output will be connected to ground (F is low) when: (B AND C are high) OR A is high F = B C + A