Top-level Verilog Designs Discussion D9.1 Example 12.

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Presentation transcript:

Top-level Verilog Designs Discussion D9.1 Example 12

Mux / 7-Segment Decoder

// Example 12: Top-level design module mux7seg ( input wire [7:0] sw, input wire s1, output wire [6:0] a_to_g ); // Intermediate signal wire [3:0] y; mux24 MUX1(.a(sw[3:0]),.b(sw[7:4]),.s(s1),.y(y) ); hex7seg d7R(.x(y),.a_to_g(a_to_g) ); endmodule

mux24 MUX1(.a(sw[3:0]),.b(sw[7:4]),.s(s1),.y(y) );

hex7seg d7R(.x(y),.a_to_g(a_to_g) );

// Example 12: Top-level design module mux7seg ( input wire [7:0] sw, input wire s1, output wire [6:0] a_to_g ); // Intermediate signal wire [3:0] y; mux24 MUX1(.a(sw[3:0]),.b(sw[7:4]),.s(s1),.y(y) ); hex7seg d7R(.x(y),.a_to_g(a_to_g) ); endmodule

Aldec Active-HDL Simulation

2-Digit / 7-Segment Display

// Example 12b: 2-digit, 7-segment display module two7seg ( input wire [7:0] sw, output wire [6:0] a_to_g, output wire [6:0] aa_to_gg ); hex7seg d7L(.x(sw[7:4]),. a_to_g(aa_to_gg) ); hex7seg d7R(.x(sw[3:0]),. a_to_g(a_to_g) ); endmodule

Aldec Active-HDL Simulation