ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 12 Circuit Analysis Procedure.

Slides:



Advertisements
Similar presentations
ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine.
Advertisements

ENGIN112 L7: More Logic Functions September 17, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 7 More Logic Functions: NAND, NOR,
1 Combinational Logic Design&Analysis. 2 Introduction We have learned all the prerequisite material: – Truth tables and Boolean expressions describe functions.
CS 151 Digital Systems Design Lecture 21 Analyzing Sequential Circuits.
ENGIN112 L8: Minimization with Karnaugh Maps September 19, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh.
08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:
CS 151 Digital Systems Design Lecture 6 More Boolean Algebra A B.
Lecture 14 Today we will Learn how to implement mathematical logical functions using logic gate circuitry, using Sum-of-products formulation NAND-NAND.
Give qualifications of instructors: DAP
ENGIN112 L13: Combinational Design Procedure October 1, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 13 Combinational Design Procedure.
CS 151 Digital Systems Design Lecture 13 Combinational Design Procedure.
ENGIN112 L5: Boolean Algebra September 12, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 5 Boolean Algebra.
CS 151 Digital Systems Design Lecture 8 Minimization with Karnaugh Maps.
Lecture 13 Problems (Mano)
Computer Organization and Assembly Language: Chapter 7 The Karnaugh Maps September 30, 2013 By Engineer. Bilal Ahmad.
ENGG 1203 Tutorial Combinational Logic (I) 1 Feb Learning Objectives
Digital Logic Lecture 08 By Amr Al-Awamry. Combinational Logic 1 A combinational circuit consists of an interconnection of logic gates. Combinational.
Overview of Chapter 3 °K-maps: an alternate approach to representing Boolean functions °K-map representation can be used to minimize Boolean functions.
KU College of Engineering Elec 204: Digital Systems Design
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 12 – Design Procedure.
Introduction to Computer Science David Goldschmidt, Ph.D. Computer Science The College of Saint Rose CIS September 6, 2007.
Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 9 – Multilevel Optimization.
9/15/09 - L7 Two Level Circuit Optimization Copyright Joanne DeGroat, ECE, OSU1 Two Level Circuit Optimiztion An easier way to generate a minimal.
Slide 1-1 Organizational Remarks I don’t use the exercises in Mano/Kime; this way you can use them as review exercises (for many of them there are solutions.
Digital Electronics Lecture 6 Combinational Logic Circuit Design.
Combination of logic gates  Logic gates can be combined to produce more complex functions.  They can also be combined to substitute one type of gate.
Abdullah Said Alkalbani University of Buraimi
Lecture 11 Combinational Design Procedure
ENGIN112 L6: More Boolean Algebra September 15, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 6 More Boolean Algebra A B.
CEC 220 Digital Circuit Design Boolean Algebra I Wed, Sept 2 CEC 220 Digital Circuit Design Slide 1 of 13.
ECE 3110: Introduction to Digital Systems Chapter #4 Review.
1 Lecture 12 More about Combinational Analysis and Design Procedures.
ECE2030 Introduction to Computer Engineering Lecture 6: Canonical (Standard) Forms Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.
EE3A1 Computer Hardware and Digital Design Worked Examples 3 Test and testability (1)
1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.
Logic Design CS221 1 st Term combinational circuits Cairo University Faculty of Computers and Information.
Designing Combinational Logic Circuits
Karnaugh Maps (K-Maps)
Combinational Circuits
THE K-MAP.
Karnaugh Maps Not in textbook. Karnaugh Maps K-maps provide a simple approach to reducing Boolean expressions from a input-output table. The output from.
C.S.Choy39 TERMINOLOGY Minterm –product term containing all input variables of a function in either true or complementary form Maxterm – sum term containing.
Karnaugh Maps (K maps).
Unit II Fundamentals of Logic Design By Roth and Kinney.
Figure 5–5 Exclusive-OR logic diagram and symbols. Open file F05-05 to verify the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by.
School of Computer and Communication Engineering, UniMAP DKT 122/3 - DIGITAL SYSTEM I Chapter 4A:Boolean Algebra and Logic Simplification) Mohd ridzuan.
Lecture 5 More Boolean Algebra A B. Overview °Expressing Boolean functions °Relationships between algebraic equations, symbols, and truth tables °Simplification.
Lecture 5: K-Map minimization in larger input dimensions and K-map minimization using max terms CSE 140: Components and Design Techniques for Digital Systems.
Circuits, Truth Tables & Boolean Algebra. Expressions Can describe circuits in terms of Boolean expression.
Programming for GCSE Topic 9.2: Circuits for Adding T eaching L ondon C omputing William Marsh School of Electronic Engineering and Computer Science Queen.
Circuit Synthesis A logic function can be represented in several different forms:  Truth table representation  Boolean equation  Circuit schematic 
Digital Logic Design. Truth Table  Logic Circuit 1. Start with truth table 2. When your output is a 1, figure out the combination of inputs, ANDs, and.
Combinational Design, Part 2: Procedure. 2 Topics Positive vs. negative logic Design procedure.
Lecture 1 Gunjeet kaur Dronacharya group of institutions.
Digital Systems Design 1 Signal Expressions Multiply out: F = ((X + Y)  Z) + (X  Y  Z) = (X  Z) + (Y  Z) + (X  Y  Z)
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-4 Verification 1Created by: Ms.Amany AlSaleh.
Logic Gates and Boolean Algebra
Prof. Hsien-Hsin Sean Lee
University of Maryland Baltimore County Department of Computer Science and Electrical Engineering   CMPE 212 Laboratory (Discussion 6) Hasib Hasan
CHAPTER 1 : INTRODUCTION
Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates,
Give qualifications of instructors: DAP
Boolean Expressions Lecture No. 10.
Computer Architecture CST 250
ECE 331 – Digital System Design
Computer Science 210 Computer Organization
BASIC & COMBINATIONAL LOGIC CIRCUIT
Laws & Rules of Boolean Algebra
Circuit Analysis Procedure by Dr. M
Presentation transcript:

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 12 Circuit Analysis Procedure

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Overview °Important concept – analyze digital circuits Given a circuit -Create a truth table -Create a minimized circuit °Approaches Boolean expression approach Truth table approach °Leads to minimized hardware °Provides insights on how to design hardware Tie in with K-maps (next time)

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 The Problem °How can we convert from a circuit drawing to an equation or truth table? °Two approaches °Create intermediate equations °Create intermediate truth tables A B C A B C’ Out

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Label Gate Outputs 1.Label all gate outputs that are a function of input variables. 2.Label gates that are a function of input variables and previously labeled gates. 3.Repeat process until all outputs are labelled. A B C A B C’ Out R S T

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Approach 1: Create Intermediate Equations  Step 1: Create an equation for each gate output based on its input. R = ABC S = A + B T = C’S Out = R + T A B C A B C’ Out R S T

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Approach 1: Substitute in subexpressions  Step 2: Form a relationship based on input variables (A, B, C) R = ABC S = A + B T = C’S = C’(A + B) Out = R+T = ABC + C’(A+B) A B C A B C’ Out R S T

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Approach 1: Substitute in subexpressions  Step 3: Expand equation to SOP final result Out = ABC + C’(A+B) = ABC + AC’ + BC’ A C’ Out B C’ A B C

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Approach 2: Truth Table  Step 1: Determine outputs for functions of input variables. A A B B C C R R S S A B C A B C’ Out R S T

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Approach 2: Truth Table  Step 2: Determine outputs for functions of intermediate variables. A A B B C C T = S * C’ R R S S T T C’ A B C A B C’ Out R S T

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Approach 2: Truth Table  Step 3: Determine outputs for function. A A B B C C R R S S T T Out R + T = Out A B C A B C’ Out R S T

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 More Difficult Example  Step 3: Note labels on interior nodes

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 More Difficult Example: Truth Table  Remember to determine intermediate variables starting from the inputs.  When all inputs determined for a gate, determine output.  The truth table can be reduced using K-maps. A A B B C C F F F’ T T T T T T F F

ENGIN112 L12: Circuit Analysis Procedure September 29, 2003 Summary °Important to be able to convert circuits into truth table and equation form WHY? ---- leads to minimized sum of product representation °Two approaches illustrated Approach 1: Create an equation with circuit output dependent on circuit inputs Approach 2: Create a truth table which shows relationship between circuit inputs and circuit outputs °Both results can then be minimized using K-maps. °Next time: develop a minimized SOP representation from a high level description