Surprise Quiz EE384Z: McKeown, Prabhakar ”Your Worst Nightmares in Packet Switching Architectures”, 3 units [Total time = 15 mins, Marks: 15, Credit is given for short answers] 1.(5pts) Find the conditions under which a centralized shared memory switch built using multiple slower parallel memories can emulate an OQ switch 2.(5 pts) For a shared memory crossbar switch, find a sufficient bound on the speedup of the crossbar, to emulate an OQ switch which performs WFQ. 3.(5 pts) Show that if the traffic to any output is leaky bucket constrained, an IQ switch, can emulate an OQ switch within a delay bound, with a speedup of 2

Using Constraint Sets to Analyze IQ Switches Sundar Iyer, Nick McKeown (sundaes, Departments of Electrical Engineering & Computer Science, Stanford University

Outline 1.Introduction 2.FIFO Scheduling 3.PIFO Scheduling 4.Comparison to Charny’s Thesis

The Constraint Set (CS) Technique A technique to analyze single buffered routers 1.Determine packet’s departure time 2.Define the Constraint’s on the system for both inputs and outputs (if applicable) –Buffer, Fabrics, Speedup etc. 3.Apply the Pigeonhole principle Constraint Sets can be used to analyze Parallel Packet Switches (FIFO, PIFO) Shared Memory with Bus Shared Memory with Crossbar Input Queued Switches.. and we expect in general any single buffered router

Characteristics of an IQ switch Arriving packets are immediately written into the input queue, on the same port as that of the switch The packet is sent to the output at or after, the time of its “ideal” departure. We shall assume that the crossbar has a speedup of “s”, where “s” is the number of packets which can be sent from one input to an output in a cell slot. Buffers Inputs Outputs

The Leaky Bucket “(  )” Regulator Tokens at rate,  Token bucket size,  Packet buffer Packets One byte (or packet) per token “(  R )”

Some Definitions M is the Leaky Bucket Size –A property of the traffic pattern –This is not in our hands K is the Relative Delay –The amount by which we can delay the departure of a cell –A property of the switch –This is in our hands, we can tweak it

Outline 1.Introduction 2.FIFO Scheduling 3.PIFO Scheduling 4.Comparison to Charny’s Thesis

Allocations as seen by the Output … DT + kDT-KDT c k Packet has a FIFO Departure Time = DT Allocated Departure Time (ADT) in (DT, DT + k) In the interval (DT, DT + k) –There is one cell which tries to get allotted in that interval. –No more than k cells get delayed and are allotted to that interval Number of Time Slots Available >= [k – k /S] The past comes to haunt you ….

Allocations as seen by the Input … DT + kDT-M-KDT c M + k DT-M Packet has a FIFO Departure Time = DT Allocated Departure Time (ADT) in (DT, DT + k) In the interval (DT, DT + k) –There is one cell which tries to get allotted in that interval –No cell which arrived before DT–M-k will be allotted to this interval Number of Time Slots Available >= [k – (k+M)/S]

Sufficiency Conditions on Speedup We are guaranteed a timeslot if –[k- k/S] + [k – (k+M)/S] > K –S > 2 + M/k Thus we can prove that –S > 2 The IQ switch has 100% throughput, by setting k  very large –S > 3 The IQ switch can emulate a FIFO-OQ switch within M slots by setting k=M

Outline 1.Introduction 2.FIFO Scheduling 3.PIFO Scheduling 4.Comparison to Charny’s Thesis

PIFO Queues – Departure Order Timeline of departures Arrival Order, Cell 8 arrives first, Cell 4 arrives last “The cell number is the name of a cell. In this figure it also represents the final departure order of these cells”

What is the problem with PIFO? 1.The CS Technique depends on being able to predict the departure time and schedule it. –The departure time of a cell is not fixed in PIFO 2.The departure time of a cell can increase –Hence, at the input we can have very old cells and cannot bound the number of cells. 3.How do we solve this problem? We shall schedule cells based on their initial departure time

PIFO Queues – Initial Departure Time (IDT) Scheduling Timeline for Departures Arrival Order, Cell 8 arrives first, Cell 4 arrives last IDT for cells

Extreme Case for IDT – Backlogged Queues Arrival Order, Cell 8 arrives first, Cell 4 arrives last Scheduling Timeline for Departures IDT for cells are shown in red

Some Properties Lemma: 1.(Weak) “If an output has a bucket size of M then no more than M cells are allotted the same initial departure time ”. 2.(Strong) If an output has a bucket size of M, then no more than M+a cells are allotted an IDT in a time interval of size a Proof: –Consider a cell arriving at time = t. –Since, the bucket size is M, it’s initial departure time is within (t, t +M) –Hence proved.

past Allocations as seen by the Output Packet has a PIFO Initial Departure Time = PT Allocated Departure Time (ADT) in (PT, PT + k) In the interval (PT, PT + k) When a cell arrives at the switch, there are no more than k + M cells waiting in the switch for that output. Unlike FIFO, future allocations can interfere by pushing in to the interval Number of Time Slots Available >= [k – (k +M)/S] … PT + k PT c future M + k

Allocations as seen by the Input … PT + kPT-M-KPT c M + k PT-M Packet has a PIFO Initial Departure Time = PT Allocated Departure Time (ADT) in (PT, PT + k) In the interval (PT, PT + k) –There is one cell which tries to get allotted in that interval –No cell which arrived before PT–M-k will be allotted to this interval Number of Time Slots Available >= [k – (k+M)/S]

Sufficiency Conditions on Speedup We are guaranteed a timeslot if –[k- (k+M)/S] + [k – (k+M)/S] > K –S > 2 + 2M/k The IQ switch has the following properties –with S > 2, has 100% throughput, even with PIFO based scheduling, set k  very large. –Can emulate a PIFO-OQ switch with with S > 3, and a relative delay of 2M with S > 4, and a relative delay of M

Outline 1.Introduction 2.FIFO Scheduling 3.PIFO Scheduling 4.Comparison to Charny’s Thesis

Anna Done it… Theorems –(Weak) If S > 4, then any maximal matching policy will give 100% throughput –(Strong) If S > 2, then any maximal matching policy will give 100% throughput. –(Stronger) If S > 2, then there is bounded emulation of a FIFO-OQ switch.

Comparison FIFO –Charny’s analysis and CS are similar Anna’s done the FIFO analysis first!  The proof using CS is much simpler though QoS –Charny does not analyze QoS scheduling –Charny uses rate controlled inputs, with FIFO scheduling to give QoS –The CS Technique directly analyzes PIFO –Note: Charny’s proofs can be modified to analyze PIFO PIRO –No one has thought of working on this before. –But in fact, PIRO can be done with CS, with LIFO allocation of departure times.

Comparison Summary Switch Algorithm –Charny’s Work: Pros: –Works for any maximal algorithm Cons: –But the matching has to be calculated –QoS not analyzed directly –CS Technique: Cons: –Works for a specific algorithm only Pros: –The crossbar scheduling is automatic –FIFO, PIFO, PIRO can be analyzed directly for IQ switches

References Anna Charny, “Providing QoS guarantees in Input Buffered Crossbar Switches with Speedup”, Sep Internal References: –Papers on Constraint Sets –PPS papers, Shared Memory Paper