Xilinx Confidential – Internal NetFPGA10G Michaela Blott, September 2010 Page 1

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx NetFPGA10G Team  Michaela Blott  Adam Covington  Jonathan Ellithorpe  Paul Hartke  John Lockwood  Nick McKeown  Sachidanandan Sambandan  Kees Vissers  Tatsuya Yabe  James Zeng Page 2

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 3 Motivation/ Objective  Leverage LATEST technology to create a networking reference platform  Enable researchers, students and customers to build working prototypes of hardware-accelerated networking systems  Upgrade interface speeds and components to facilitate faster and more complex prototypes  Successor to the highly successful networking research platform NetFPGA - used by over 500 universities worldwide

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 4 High-Level Specification Xilinx Virtex5 XCV5TX240T-2 FG1759 1G or 10G Ethernet subsystem PCIe x8, Gen1 interface QDRII SRAM subsystem High-speed serial expansion interface RLDRAMII CIO DRAM subsystem PCIe adapter full size card, dual slot with extra ATX power connector Standalone operation supported 1G or 10G Ethernet subsystem Page 4 V2

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 5 Memory Interface - SRAM Subsystem –QDRII, 300MHz, CY7C1515JV18-300BZXC –overall density 216Mb –organized in 3 independent 36bit interfaces –64.8Gbps raw access for read and 64.8Gbps for 300MHz –sized to handle flow classification, routing table lookup, flow statistics, and free and used lists SRAM adr, ctldin dout 36bit SRAM adr, ctldin dout 36bit SRAM adr, ctldin dout 36bit Page 5

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 6 Memory Interface - DRAM Subsystem RLDRAMII CIO adr, ctldata adr, ctldata RLDRAMII CIO 2*32=64bit –RLDRAMII CIO, MHz, MT49H16M36HT-25:A –overall density 2.3Gb (57msec storage of 40Gbps traffic) –arranged as 2 independent 64bit interfaces (2 components per interface) –76.8Gbps shared raw access for read and 300MHz –sized to handle packet buffering 2*32=64bit Page 6

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 7 Network Interface Flavours  PHY: four single-port PHYs (NetLogic AEL2005)  10G interfaces or 1G interfaces via SFP+ cages  Supported physical standards: –10G direct attach copper, and optical interfaces 10G LRM, 10G SR, 10G LR –1000BaseT and 1000BaseX SFP+ cage 10G PHY SFI XAUI FPGA XAUI 10G PHY XAUI 10G PHY Page 7

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 8 Expansion Connector  purpose: –allow greater port density, –support different physical interface flavours –add daughter cards with extra memory cards or NSEs/ KBPs  2 flavours: –daughter card expansion –board to board with expansion cable  connector: –Two QTH Samtec connectors –Designed for XAUI, PCIe, SATA, Infiniband, HyperTransport, etc.  board to board cable: –Twinax micro-ribbon cable –Available in different lengths: for example 0.5m (100 Gbps);1m (50 Gbps) –recommended part number: HQDP STL-SBR-2 FPGA Samtec connector distance vs speed: Page 8

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 9 NetFPGA 1GNetFPGA 10G 4 x 1Gbps Ethernet Ports 4 x 1Gbps or 4 x 10Gbps Ethernet Ports 4.5 MB ZBT SRAM 64 MB DDR2 SDRAM 27 MB QDRII-SRAM 288 MB RLDRAM-II PCIPCI Express x8 Virtex II-Pro 50Virtex 5 TX240T NetFPGA1G – 10G comparison In a nutshell... Page 9

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 10 FPGA Designs  Stress-test design  prove the board is functional under maximum load (temperature, power, noise)  Basic & full infrastructure designs  provides basic RTL infrastructure to all users in form of well-defined and abstracted interfaces  Planned reference designs  PCIe-ICAP design (allows configuration of the FPGA via PCIe)  Stanford reference router design  HLS platform  and others... Page 10

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 11 More information... Page 11  Alpha Program  Pricing is still being negotiated – heavily subsidized for academics as Micron, Cypress, NetLogic Microsystems and Xilinx are donating the parts  Board was built in collaboration with Hitech Global, who will also distribute the board: (for academic and commercial use) Visit HiTechGlobal’s website –  Status: Release to Manufacture in the next weeks  Visit NetFPGA website for the latest update –  If you haven’t already, sign up to netfpga-announce mailing list –

Xilinx Confidential – Internal THANK YOU! Page 12

Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Page 13 Demo Stress-test Design QDR memory test RLDRAM memory test PCIe test SFP+ test UART report PCIe Application & Driver Hyperterminal Host CPU FPGA Test computer Config & Flash test Clock & PWR test Config & Flash test CPLD NetFPGA10G board Filler