Integration of Retiming with Architectural Floorplanning: A New Design Methodology for DSM Abdallah and Bassam Tabbara Profs: R.K.Brayton, A.R.Newton, and K.Keutzer The NexSIS Project

2 Issues in DSM timing at the module level not an issue timing at the chip level is an issue bigger raw capacity that can be used by: àreplication àreuse NTRS Projections: à1997:.25u4M tr/cm pins6 layers 3cm 2 à2006:.1u40M tr/cm pins8 layers 10cm 2

3 Problem Description one-level hierarchy of design àminimum number of levels to support reuse àmid way between flat and two level placement and wireplanning of: à modules, average size: 50k gates àdynamic range of modules sizes: 1-500k gates àtypes of modules: hard, firm, soft hard: layout firm: gates + aspect ratio soft: RTL àlarge number of nets: 40k-100k àpins per module:

4 Problem Statement We address chip level assembly of predesigned IP blocks, each under 100k gates in size, either as hard or soft macros, optimizing for performance, power and area (emphasis in that order).

5 Goals develop a tool that has an impact in DSM by supporting IP reuse handle IP blocks that have constraints and should be combined to result in a certain functionality. User design constraints include: àdelay àpower dissipation àarea generate a final layout within hours (overnight) àcomplexity of algorithms within O(m 2 ) -O(m 3 ) m = design complexity final result should: àbe within 5-10% of human design (may not be able to compare) àmeet the user constraints if possible or make design suggestions

6 Challenges size issues: àbigger block sizes, aspect ratios and relative sizes ànumber of pins, nets much bigger than blocks placement issues: àspecial design for memories? àpartitioning hard, clustering easy routing issues: àno channels, point to point àbusses àmany metal layers to be assigned àtiming at the chip level

7 Conventional Flows integration of various steps and tools: àLogic Synthesis - Physical Design àGlobal - Detailed separation of concerns: àfront end - back end àno contract separation entails hundreds of iterations: ànumber of iterations can be proportional to complexity of design

8 Conventional Flow Architecture

9 New Design Flow minimize design iteration: àplanning at the early stages of the flow àsupport incremental changes àneed for a proof of convergence introduce retiming into the architectural floorplanning stage àbetter handle on timing issues àpath-based vs. net-based

10 Design Flow Architecture

11 Functional Decomposition provides an entry point for reused IPs àRTL may already be well characterized àarea-delay trade-off as an important performance characteristic result is: àa set of blocks àsome area-delay trade-off estimates

12 Retiming takes in lower bound constraints creates upper bound constraints reduces area of modules whenever possible can be made refinable and incremental àdepends on granularity of the representation path-based

13 Placement / Routing initial placement/routing step àcan be a min-cut or any constructive approach àhas to be fast àgives lower bounds on delays between modules placement/routing: àtakes in upper bounds from retiming as flexibility on placement àreplaces modules resulting in better lower bound constraints àobjective is to reduce total chip area àdelay is reduced indirectly

14 Logic Synthesis assumption: àproblems can be solved at the module level àpredictable for given size modules can be run in parallel for the different modules provides better estimates of area-delay trade-offs for subsequent iterations

15 Iterations loop between placement and retiming àuntil no further improvements are possible àmay iterate many times àvery similar to: initial min-cut partitioning low temperature simulated annealing àhave to prove some convergence criteria loop between floorplanning/wireplanning and layout àonly a few iterations àeach iteration information is retained through area-delay trade-offs àalso proof of convergence