Group M3 Jacob Thomas Nick Marwaha Darren Shultz Craig LeVan Project Manager: Zachary Menegakis February 2,2005 MILESTONE 3 Size estimates/Floorplan DSP 'Swiss Army Knife' Overall Project Objective: General purpose Digital Signal Processing chip

STATUS Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (90%) To Be Done Structural Verilog Reengineering Control Logic Low-Level Modules Schematic Verification

MARKETING UPDATE How Does Our Circuit Fit Into the Bigger Picture? Focus on Audio/Video Applications Audio: Digital Radios / MP3 Players (i.e. Motorola, Lucent, Texas Instruments) Digital Music Synthesis / Sampling (i.e. Yamaha, Korg) Noise Reduction (i.e. Dolby) Video: Comb Filter to separate color and brightness (i.e. Sony, Toshiba) Others: Motor Control Functions such as RPM (i.e. Ford, GE)

MARKETING UPDATE cont Highlighted Areas Contain Many Instances of our Circuit Key Functions used: Integrators and Filters REUSE !!!!

MARKETING UPDATE cont A Moving Averager Smoothes a Signal to Reduce Noise

DESIGN DECISIONS Finalized bit-width to 12-bit floating point Based on CMU Research in Voice Recognition Complexity => Our Applications in Audio and Video 6-bit exponent, 5-bit fraction Additional Precision cannot be discerned by humans Reduces Power Consumption Increased bit-width does not add to quality/versatility Chip Applications would benefit from low power consumption Size offers advantages of parallel processing to increase speed Serial (software) vs. Parallel (hardware) operations

DESIGN DECISIONS cont

Namea0a1a2b0b1b2c1N 1Differencer100100x 2Integrator x 3Leaky Integrator x 4Comb Filter Bandpass Filter CIC Interpolation Filter dc Bias Removal1a.b0100x 8First-Order Equalizer1a.b0 100x 9Audio Comb10a.b1000x 10Moving Averager1101/N Second-Order IIR Filter1a.bbb a.bbbba.bbb 0x 12First-Order Delay Network1a.bbb 10x 13Second-Order Delay Network1a.bbb 10x 14Real Oscillator12cos(x)10 xx 15Second-Order Equalizer1(a.b*cos(x)a.b1a.b*cos(x)1/a.b0x 16Real FSF, Type I12cos(x)?*cos(x) 01x/2*pi*k 17Real FSF, Type IV12cos(x)?*10 1x/2*pi*k 18Complex FSF1imag01001x/2*pi*k 19Quadrature OscillatorG(n)imag0100xx 20First-Order IIR Filter1imag01 00x 21Goertzel Network12cos(x)1imag00x/2*pi*k 22Sliding DFT Networkimag10100r^Nx/2*pi*k

FLOORPLAN Each block is approximately 100 * 100 with the exception of the possibly larger comb filter

FLOORPLAN alternative

POROSITY STOLEN FROM W (Thanks Myron & Bobby)

SIZE ESTIMATES Adder: 5 * ( ) = 2500 Mult: 7 * ( ) = 8000 Div: 2 * ( ) = 2400 Fmult: 1 * (1200) = 1,200 Misc: ( ) = 2,000 Registers: 83 * ~22 = 1,900 18,000 transistors

VERILOG

PROBLEMS & QUESTIONS Determine Bit Width Floorplan – Minimize Comb Filter or use Alternative? Should Focus Be Area or Global Routing? Structural Verilog Fix Control Logic within Basic Blocks