CSE 140 Lecture 15 System Designs Professor CK Cheng CSE Dept. UC San Diego 1

System Designs Introduction Components Spec Implementation 2

I. Introduction Data Subsystem Control Subsystem Conditions Control Signals 64 Data Inputs Control Inputs Data Outputs Control Outputs go done (ready) 3

Data Subsystem Control Subsystem Components Storage Modules Operators Interconnections Sequential machines Functions Data storage Data transformation Control of data transfers Control of transformations Control of the sequential system 4 Introduction

Components Storage Operator Interconnect 5

Components: Storage Modules, Register LD CLR D Q CLK Q(t+1) = (0, 0,.., 0)if CLR = 1 = Dif LD = 1 and CLR = 0 = Q(t)if LD = 0 and CLR = 0 6

Storage Component: Registers, Array of Registers LD c R D Array of Registers: Sharing connections and controls c R D Decoder address 7 Registers: If c then R  D

Decoder RAM Address Size of RAM larger than registers FIFO (First in first out) LIFO (Stack) 8 Storage Components: RAM, FIFO, LIFO RAM

Functional Modules A B Z Operation selection CASE Op-Sel Is When F1, Z <= A op1 B When F2, Z <= A op2 B. End CASE 9

Interconnect Modules (Wires and Switches 1. Single line (shifting, time sharing) 10 Single Lines Band of Wires Shared Buses Crossbar

2. Band of Wires (BUS) 3. Shared Bus R1R2R3Rm ….. c y x x y cd N MUX DEMUX 11 Switches switch

4. Crossbar (Multiple buses running horizontally) m simultaneous transfers are possible, but more expensive. 12 MUX … Bus 1 64 Bus m R1 Rm

Program: 1.Objects (Registers, Outputs of combinational logic) 2.Operation 3.Assignment 4.Sequencing Example: Signal R1, R2, Bit Vector V (15 down to 0); Z  A + B ( A, B, Z need to be defined) R1  R2 Begin End if ( ) then ( ), ENDIF; 13

Ex. If C then R1  S1 Else R2  S2 Endif; R1 LD R2 S2 S1 C If C1 then X  A Else X  B + C Endif If C2 then G  X Endif MUX 1 0 Adder BCA G C1 C2 CLK 14