NoC, NoC! Who's there? Rabi N. Mahapatra Texas A&M University

July 15, 2015Rabi N. Mahapatra - IIT Delhi2 Agenda Why NoCs? What are NoCs? NoC Research Areas NoC TAMU Core Network Interface Architecture Design Concurrent On-Line Testing (COLT) in NoC- based SoCs Useful Resources Summary

July 15, 2015Rabi N. Mahapatra - IIT Delhi3 Why NoCs? Era of multi-core SoCs Communication intensive applications Bus-based communication infrastructures suffer from scalability, predictability and performance limitations

July 15, 2015Rabi N. Mahapatra - IIT Delhi4 What are NoCs? Networks-on-a-Chip (NoC) are essential Features: Higher availability Easier power management Higher performance Predictable operation

July 15, 2015Rabi N. Mahapatra - IIT Delhi5 Typical NoCs Regular topologies Simple non-blocking routing

July 15, 2015Rabi N. Mahapatra - IIT Delhi6 Some NoC Research Areas Application Mapping Architecture design and synthesis Fault Tolerance Flow control/congestion control Power management On-chip routing NoC Testing Core Interfacing Communication reliability

July 15, 2015Rabi N. Mahapatra - IIT Delhi7 NoC Research Summary Over 29 Academic Institutions worldwide Industrial Companies Arteris ( ST Microelectronics Intel Over 800 publications…and counting.

July 15, 2015Rabi N. Mahapatra - IIT Delhi8 NoC TAMU Mapping heuristic for communicating resources to target regular topology On-chip communication reliability FEC in NoCs Core-Network Interface Architecture Concurrent On-Line Testing (COLT) in NoCs Peak Power Management in NoCs

Core-Network Interface (CNI) Architecture Design

July 15, 2015Rabi N. Mahapatra - IIT Delhi10 Core-Network Interface (CNI) IP cores have two types of interfaces Standard interfaces: OCP-IP, VSIA, etc Non-standard/in-house interfaces: proprietary to a particular corporation NoCs have differing configurations too! Topology, routing policies, flow control, reliability configuration.

July 15, 2015Rabi N. Mahapatra - IIT Delhi11 CNI CNI lets IP cores talk the language of NoC Basic operation: Packetization De-packetization

July 15, 2015Rabi N. Mahapatra - IIT Delhi12 Related Research CNI first studied in BhojwaniVLSID’03 Packetization cost assessment for 3 techniques: software, hardware wrapper and on-chip co-processor (Xtensa)

July 15, 2015Rabi N. Mahapatra - IIT Delhi13 CNI Requirements Need for a customizable CNI architecture IP core interface On-chip communication reliability NoC configuration Additional features Dynamic power/thermal management IP core test support NoC reconfiguration

July 15, 2015Rabi N. Mahapatra - IIT Delhi14 CNI Architecture [Bhojwani ISQED’06]

July 15, 2015Rabi N. Mahapatra - IIT Delhi15 CNI Architecture Interface Arbiter Replays interface protocols of the IP Cores Receives and forwards communication request and responses

July 15, 2015Rabi N. Mahapatra - IIT Delhi16 CNI Architecture Link Controller Interfaces to on-chip router Receives and forwards flits from and to NoC

July 15, 2015Rabi N. Mahapatra - IIT Delhi17 CNI Architecture Encoder and Decoder Provide end-to-end communication reliability via coding schemes Support for ED+R, FEC

July 15, 2015Rabi N. Mahapatra - IIT Delhi18 CNI Architecture Packetizer and De-packetizer Prepare and extract data to and from flits

July 15, 2015Rabi N. Mahapatra - IIT Delhi19 CNI Architecture CNI Controller Manages CNI data-paths Responsible for issuing NoC management commands

July 15, 2015Rabi N. Mahapatra - IIT Delhi20 CNI Architecture Communication Scheduler (CNI-CS) Sets QoS parameter for on-chip communication Power Manager (CNI-PM) Manage communication power with injection control

July 15, 2015Rabi N. Mahapatra - IIT Delhi21 CNI Architecture Test Controller Interface to Test Wrapper of attached IP cores

July 15, 2015Rabi N. Mahapatra - IIT Delhi22 CNI Analysis IP Core interface: OCP-IP 2.0 compliant NoC configuration: 4x4 2D folded torus Source routing SystemC functional model integrated into NoCSim

Concurrent On-Line Testing (COLT)

July 15, 2015Rabi N. Mahapatra - IIT Delhi24 Why Test Concurrently ? Design complexity Noise margins Some sources of failure: Electro-migration, stress migration, time- dependent dielectric breakdown, thermal cycling. Reducing lifetimes Need to assess system health before recovery schemes can be activated

July 15, 2015Rabi N. Mahapatra - IIT Delhi25 On-Line Test What do we mean by OLT? In-field confidence in the correct functional operation of the system Precursor to reconfiguring system to address a fault Can by achieved at 100% overhead by using a parallel execution stream for comparison! Our goal to keep it much lower Possibly < 10%! But at other costs…

July 15, 2015Rabi N. Mahapatra - IIT Delhi26 On-Line Test Challenges Test cost Test power (up to 2x) Test time Test volume These make on-line test management a challenge!

July 15, 2015Rabi N. Mahapatra - IIT Delhi27 On-Line Testing in Research Manufacturers insert Infrastructure IP (I-IP) into SoC to improve yield and to provide test support within designs Reuse these I-IPs to perform the on-line SoC test

July 15, 2015Rabi N. Mahapatra - IIT Delhi28 OLT in Research Detect idle periods of execution and test SoC components using I-IPs  non- concurrent on-line testing But detecting the idle periods is a challenge itself! Another option is needed!

July 15, 2015Rabi N. Mahapatra - IIT Delhi29 Concurrent On-Line Test Concurrent On-Line Testing (COLT) Test in the presence of executing applications No need to “turn off” applications Challenges to COLT Test + Application  under power budget Test has to be restorative in nature Test Intrusion into Application has to be minimized

July 15, 2015Rabi N. Mahapatra - IIT Delhi30 Test Infrastructure IP (TI-IP) Introduce a Test Infrastructure-IP (TI- IP) into the SoC to manage COLT Use the NoC as Test Access Mechanism (TAM) Manage test intrusion  challenge! [Bhojwani ISQED’07]

July 15, 2015Rabi N. Mahapatra - IIT Delhi31 Conceptual NoC enabled SoC + TI-IP

July 15, 2015Rabi N. Mahapatra - IIT Delhi32 Proposed TI-IP Architecture TI-IP Components Input/Output Queues Test Memory TI-IP Engine

July 15, 2015Rabi N. Mahapatra - IIT Delhi33 COLT in Action CNI determines when IP core test is required Request sent to TI-IP TI-IP determines if OLT of IP core is feasible Involves System Snapshot Collection, Test Vector Routing, Test Scheduling

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July 15, 2015Rabi N. Mahapatra - IIT Delhi36 Multi TI-IP Configuration COLT has to be scalable Proximity of TI-IP affects test power consumption

July 15, 2015Rabi N. Mahapatra - IIT Delhi37 Multi TI-IP Multiple TI-IPs in NoC working co- operatively TI-IP testing is needed too Token Ring of TI-IPs helps in addressing this challenge

July 15, 2015Rabi N. Mahapatra - IIT Delhi38 Robust COLT Protocol Robust protocol is essential Identify potential hazards Embed mitigation techniques into COLT Protocol

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July 15, 2015Rabi N. Mahapatra - IIT Delhi40 Experimental Setup Two SoC configurations built around NoCSim Embedded System Synthesis Benchmark Suite (E3S) provide application configuration ITC’02 SoC Test Benchmarks provide SCAN test configuration information Only considering SCAN for now due to test data availability Only testing IP cores (for now)

July 15, 2015Rabi N. Mahapatra - IIT Delhi41 Experimental Setup Assign 1 TI-IP to an SoC and let it occupy a whole NoC tile For a 22mm x 22mm chip laid out as a 4x4 2D torus, each tile could be 5mm x 5mm [Towles DAC’01] 5.2% area overhead Multi TI-IP configurations also prepared and validated in NoCSim environment

July 15, 2015Rabi N. Mahapatra - IIT Delhi42 Test Configurations Each network tile consists of an IBM 405GP. (area constraints) Task graph assignment done by hand.

July 15, 2015Rabi N. Mahapatra - IIT Delhi43 Results

July 15, 2015Rabi N. Mahapatra - IIT Delhi44 Results

July 15, 2015Rabi N. Mahapatra - IIT Delhi45 Test Throttling response to misbehaving applications Energy profile demonstrating TI-IP Test Throttling effect on misbehaving application

July 15, 2015Rabi N. Mahapatra - IIT Delhi46 COLT Protocol – Avoiding Starvation Energy profile demonstrating starvation hazard mitigation

July 15, 2015Rabi N. Mahapatra - IIT Delhi47 TI-IP Synthesis Results With Synopsys Design Compiler using Virginia Tech VLSI for Telecommunications TSMC-0.25um, 2.5V standard cell library Gate Count: 83K Power: 520mW Leakage: 32uW

July 15, 2015Rabi N. Mahapatra - IIT Delhi48 Summary Multi-core systems are here to stay Address communication challenges with NoCs Interfacing with a variety of IP cores require the use of a generic CNI architecture Lowering reliability under higher costs of testing requires concurrent on-line test of on-chip components

July 15, 2015Rabi N. Mahapatra - IIT Delhi49 Summary Need for COLT benchmarks

July 15, 2015Rabi N. Mahapatra - IIT Delhi50 Useful Resources On-Chip Network Research Resources Page