DFT Technologies for High- Quality Low-Cost Manufacturing Tests Yuval Snir JTAG 2006 Yuval Snir JTAG 2006.

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Presentation transcript:

DFT Technologies for High- Quality Low-Cost Manufacturing Tests Yuval Snir JTAG 2006 Yuval Snir JTAG 2006

AgendaAgenda Background – Two major fault models Background – Two major fault models Problem – Exploiting a given tester memory Problem – Exploiting a given tester memory Main goal – Two effective implementation Main goal – Two effective implementation solutions solutions

BackgroundBackground The Shrinkage of semiconductor devices brought a new distribution of defects The Shrinkage of semiconductor devices brought a new distribution of defects Timing defects have become more significant (at least 2% of all defects) Timing defects have become more significant (at least 2% of all defects)

BackgroundBackground For 130 nm fabrication For 130 nm fabrication Of yield 70% Of yield 70% No statistical faults No statistical faults Defect rate will be 0.7% Defect rate will be 0.7% 7000 defective devices 7000 defective devices un detected per million un detected per million (DPM) (DPM)

Fault Models Stuck-at fault-model: Stuck-at fault-model:  the most popular fault model used in practice  a line whose status is stuck at a given value (normally 0 or 1). abccc > >01 -b -b true

fault Models At-speed fault model: At-speed fault model:  Example: InitializationB=1 Opposite value Propagates from B to C

The Problem Desired fast & low cost technologies tests Desired fast & low cost technologies tests Transition pattern set is 3-5 bigger then Transition pattern set is 3-5 bigger then stuck-at pattern set stuck-at pattern set Sometimes there isn’t enough room on the tester memory for both pattern sets. Sometimes there isn’t enough room on the tester memory for both pattern sets. Yields expensive tester reloads of the memory. Yields expensive tester reloads of the memory.

1. Effective Merging At-Speed with Stuck-At Patterns 1. Effective Merging At-Speed with Stuck-At Patterns 2. EDT – Embedded Deterministic Test 2. EDT – Embedded Deterministic Test solutionssolutions

Merging At-Speed with Stuck-At Patterns Sets The TDF (Transition delay fault) patterns also detect a significant percentage of stuck-at faults The TDF (Transition delay fault) patterns also detect a significant percentage of stuck-at faults Truncate TDF patterns Truncate TDF patterns

Merging Patterns – Example Design Characteristic of the design  The tester can hold up to 10,000 test pattern  The highest priority – best possible coverage for  One TDF pattern set for each clock domain and one For cross clock domain. Design demands:

Merging Patterns Test generation results before optimization  Due to the typically slow operation of the tester The TDF test coverage is only 85.14%.

Merging Patterns Test generation results before truncation & optimization

Merging Patterns Flow for generating higher coverage:  Arrange TDF test patterns from most significant to least  Truncate TDF patterns ( 90% of the overall achievable)  Fault grade the truncated TDF patterns for SAF  Generate top-off SAF pattern set

Merging Patterns Test generation results after truncation & optimization

Merging Patterns Test generation methodology comparison

EDT-Embedded deterministic test Two additional blocks to the traditional ATPG:  Decompressor  Compactor

EDT-Embedded deterministic test  The blocks are in the scan chain path  System core isn’t affected  Immunity for logic changes  Tester see the original design

EDT-Embedded deterministic test The decompressor:  Only 1% - 5% of scan cells get specified  EDT – compression is done prior to random fill  Shorter Chains - fewer cycles and data  Less costly tester can be used Attributes: Extremely high encoding capacity, low silicon area And high speed of operation

EDT-Embedded deterministic test The compactor:  Ability to handle any number of X values  Support for production diagnostics directly from the compressed patterns

EDT-Embedded deterministic test example:  Same coverage  Effective reduction of 100X in data volume and test time  One ATPG scan pattern occupies vectors One EDT scan pattern occupies 80 vectors only!

I have to go now I have to go now