1 Tuesday, July 04, 2006 "Programs expand to fill the memory available to hold them." - Modified Parkinson’s Law.

2 Contiguous allocation §Suffers from external fragmentation §Compaction is time consuming §Used in earlier batch systems §What if a process needs to grow beyond the partition allocated to it?

3 Paging §Permit address space of processes to be non-contiguous.

4 Paging – Hardware support §Pages and frames §Page number and offset §Internal fragmentation

5 Address Translation Architecture

6 §Why are page sizes powers of two?

7 §Every memory access has to go through the page table. §Hardware page table l Limited number of entries §Paging increases context switch time

8 Implementation of Page Table §Page table is kept in main memory. §Page-table base register (PTBR) points to the page table. §Context switch time compared to hardware page table.

9 Implementation of Page Table §In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. §Solution: fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs).

10 Paging Hardware With TLB

11 TLB §Context switch §Address space IDs

12 Effective Access Time §Associative Lookup =  time unit §Assume memory cycle time is 1 microsecond §Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers. §Hit ratio = 

13 Effective Access Time §Associative Lookup =  time unit §Hit ratio =  §Effective Access Time (EAT) EAT = (1 +  )  + (2 +  )(1 –  ) = 2 +  – 

14 Page Table Size §Internal fragmentation §Unused program in memory §Page table size l Hardware page table §Transfers to and from disk

15 Memory Protection §Memory protection implemented by associating protection bit with each frame. §Valid-invalid bit attached to each entry in the page table: l “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page. l “invalid” indicates that the page is not in the process’ logical address space.

16 Valid (v) or Invalid (i) Bit In A Page Table

17 Two-Level Paging Example §A logical address (on 32-bit machine with 4K page size) is divided into: l a page number consisting of 20 bits. l a page offset consisting of 12 bits. §Since the page table is paged, the page number is further divided into: l a 10-bit page number. l a 10-bit page offset.

18 Two-Level Paging Example §Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table. page number page offset pipi p2p2 d 10 12

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20 Address-Translation Scheme §Address-translation scheme for a two- level 32-bit paging architecture

21 Inverted Page Table §One entry for each real page of memory. §Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page. §Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.

22 Inverted Page Table Architecture

23 Hashed Page Tables §Common in address spaces > 32 bits. §The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. §Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

24 Hashed Page Table

25 Shared Pages Example

26 Virtual Memory That is Larger Than Physical Memory

27 Transfer of a Paged Memory to Disk Space

28 Valid-Invalid Bit §With each page table entry a valid– invalid bit is associated (1  in-memory, 0  not-in- memory) §Initially valid–invalid bit is set to 0 on all entries.

29 Valid-Invalid Bit §Example of a page table snapshot. During address translation, if valid– invalid bit in page table entry is 0  page fault  Frame #valid-invalid bit page table

30 Page Table When Some Pages Are Not in Main Memory