Week 3- slide 1 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-Map Method Examples F = A asserted, unchanged B varies G = B’,

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week 3- slide 1 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-Map Method Examples F = A asserted, unchanged B varies G = B’, unchanged A varies Cout = F(A,B,C) = A B A B A B A B Cin AB C A B

week 3- slide 2 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-Map Method Examples F = A A asserted, unchanged B varies G = B’ B’, unchanged A varies Cout = A B + B Cin + A Cin F(A,B,C) = A A B A B A B Cin AB C A B

week 3- slide 3 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification More K-Map Method Examples, 3 Variables F' = F' -> simply circle the zeros 00 C AB A B C AB A B 0 1 F =

week 3- slide 4 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-map Method Examples: 4 variables F = AB C CD A D B

week 3- slide 5 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-map Method Examples: 4 variables F = C + A' B D + B' D' Find the smallest number of the largest possible subcubes that cover the ON-set AB C CD A D B

week 3- slide 6 EE 231 Digital Electronics Fall 01 Gate Logic: Incompletely Specified Functions n inputs -> 2 n possible input configurations for a given function, not all input configurations may be possible this fact can be exploited during circuit minimization! E.g., Binary Coded Decimal Digit Increment by These input patterns should never be encountered in practice associated output values are "Don't Cares" Off-set of W On-set of W Don't care (DC) set of W

week 3- slide 7 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification K-map Example: Don't Cares F = w/o don't cares F = w/ don't cares Don't Cares can be treated as 1's or 0's if it is advantageous to do so AB X0 11X X C CD A D B

week 3- slide 8 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification Design Example: Two Bit Comparator Block Diagram and Truth Table A 4-Variable K-map for each of the 3 output functions

week 3- slide 9 EE 231 Digital Electronics Fall 01 Gate Logic: Two-Level Simplification Design Example: Two Bit Comparator F1 = F2 = F3 = AB C CD A D B K-map forF 1 AB C CD A D B K-map for F 2 AB C CD A D B K-map forF 3