The World Leader in High Performance Signal Processing Solutions Audio ADC/DACs Primer David Hossack

2 Goals  Learn about a real world signal processing application There are hundreds of these in this room….. Also on DSP Board  Learn about commercial considerations Ask  Agenda Start at actual A/D conversion Motivate sigma-delta modulator Motivate interpolation and decimation filters Example filters  No equations – simple overview  Ask questions

3 Audio Codec on DSK physically large package by today’s standards

4 Analog/Digital Signal Conversion  Converting two things: Continuous Time Discrete Time  Sampling Sample rate – samples/s or “Hz” – eg 44.1kHz or 48kHz Need clock for discrete time  Concern on clock jitter at interface between discrete-to-continuous Continuous Value Discrete Value  Quantization Number of levels or number of bits – eg 16bit or 24bit  These conversions can happen separately Eg Switched capacitor DAC  Digital (discrete time, discrete value)  -> analog, discrete time Continuous time, but still sampled  -> analog, continuous time  Not necessarily a one-to-one transformation between input samples and output samples

5 Typical Specs for Audio Converters  SNR – measure of additive noise dB “A-weighted” Bandwidth  20-20kHz  THD – measure of errors at harmonics of input – nonlinearity dB  These are “AC” Specs  “Traditional” converter specs not appropriate Absolute accuracy Integral non-linearity Differential non-linearity Conversion Time

6 What does 100dB mean?  “CD quality” N= 16 bits => approx 6N + 2 => 98dB  With assumptions regarding the signal and error pdfs  Flat weighting, full bandwidth 1 part in %  Component matching on silicon 1% easy, with care : 0.1% >12 bits usually requires calibration or signal processing  Need to be careful to determine how errors manifest  For audio: Absolute accuracy is not important Linearity fairly important Noise very important  Hard to design audio converter using only component matching Sigma-Delta Modulation is a signal processing method to solve this Introduces its own problems  Oversampling  Out of Band Noise  Non-linear system that is hard to fully analyze Errors Specs: Offset Gain Linearity Noise

7 Sigma Delta Modulation  Method for obtaining high resolution signal conversion without requiring high component matching Quantizes input to small number of levels Signal detail is preserved and obtaining by filtering  Requires signal processing  Requires oversampling, requires sample rate conversion filters ADC – decimation (downsampling with filtering) DAC – interpolation (upsampling with filtering)  Economics limited adoption until approx 1990 Moore’s law allowed the DSP implementation to be cost effective  In engineering, the “rules” and constraints are always changing Implementations have changed significantly over the years

8 Almost all audio converters use Sigma Delta Modulation  Delta Sigma ≡ Sigma-Delta  Other applications of Sigma-Delta Modulator Based Converters: Communications  Cell Phones  Quantizer Memoryless Non-Linear Function  Loop Filter Quantization decisions affect future quantization decisions Has effect of making the quantizer behave more linearly  Oversampling 128x typical 48kHz x 128 => 6.144MHz  SigmaDelta Modulator Loop Loop Filter Coarse quantizer Quantization error are made to appear at high frequencies Desired signal is at low frequencies

9 One bit vs Multi-bit In the one-bit D/A converter, clock jitter in the over sampling clock translates directly into D/A errors - causing gross errors, increasing noise and reducing the sound quality. In a multibit sigma-delta made up of multiple two-level D/A converters, the D/A output looks more like an analog signal, making it less sensitive to jitter and easier to filter.

10 Linear Signal Processing Model of SDM  Replace quantiser by a linear gain What gain value for two level quantizer  Noise Transfer Function (NTF) The shape of the quantization noise Most of the energy is at high frequencies  Signal Transfer Function (STF) The transfer function from the input to the putput Can be flat (delay or no delay)  See books, Matlab SDM Toolbox

11 Sigma-Delta DAC  Two Level DAC No matching problems Errors are gain, offset Horrible out of band noise Non-linearities due to inter symbol interference and slew rate limiting  Multilevel DAC  Implementations Switched Capacitor  Continuous amplitude, discrete time filter Current Source

12 Multi Level DAC

13 SDM DAC Stages  Digital Interpolation 2x Interpolator  Upsample by 2  Halfband (FIR)  Allpass based structure (IIR) 2x Interpolator  Upsample by 2  Halfband (FIR)  Allpass based structure (IIR) CIC Interpolator  Often Linear Interpolator Sinc 2 Also need CIC compensation filter  Digital Sigma Delta Modulator  Digital Dynamic Element Matching Also designed using sigma-delta techniques  Analog DAC 128x 1x → 2x 2x → 4x 4x → 128x → 17 levels → 16 of 2 level

14 SDM ADC Stages  Analog Sigma Delta Modulator 2-17 Levels (1-16 decision thresholds)  Digital Decimation CIC  Down Sample by 32  Sinc 4 2x Decimator  Down Sample by 2 Halfband (FIR) Allpass based structure (IIR) 2x Decimator  Down Sample by 2 Halfband (FIR) Allpass based structure (IIR) Also need CIC compensation filter 128x 128x → 4x 4x → 2x 2x → 1x

15 CIC Filter  Recursive Filter Structure – yet FIR Pole / Zero Cancellation Need to use modulo arithmetic  Efficient for Interpolation and Decimation  Very good transfer function for large rate changes Interpolator – images of signals near dc are suppressed Decimator – frequencies that will alias to near DC suppressed  Very simple implementation Graphic from wikipedia

16 Many diagrams taken from this paper:

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20 Component Responses – Continuous Coefficients FIR1 FIR2 Sinc 2

21 Digital Filter Implementation  Use CIC filters at higher sample rates Cost efficient structure for implementing restricted set of FIR filters  Use FIR/IIR Filters at lower sample rates Exploit structural symmetries  Eg Half band FIR interpolator uses input samples directly Eg Half-band or parallel all-pass filters  Restricted responses Compensation required for CIC filters  CIC often implemented flat  FIR/IIR usually implemented by a simple DSP engine Fixed program – hardwired in logic Single multiplier or multiplier equivalent Eg Canonic Signed Digit / Signed Power of Two “multiplierless” Multiple channels implemented by single DSP engine  Cost/Power important – not on digital process Eg 0.35u or 0.18u rather than say 65nm or 45nm for analog reasons

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25 Signal Processing Design and Optimization  Oversampling Rate for Analog Converter  Number of levels for Analog Converter  Filter architecture Number of Stages Type (CIC/FIR/IIR) of stage  Limit Memory Requirement  Limit Coefficient Wordlength or number of CSD/SPT terms Affects filter response <16 bit typical  Limit Data Wordlength requirement Affects SNR, quantization effects bit typical  No floating point!

26 Signed Power of Two Coefficients  Digitally “easy” coefficients 0 +1, -1 +1/2, -1/2 +1/4, -1/4 …  Sums of these Eg +1/2 – 1/16 + 1/128  Compare with Booth encoding used in multipliers Only need a fixed set of coefficients Less general – opportunity to optimize

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28 A very simple DSP One FIR tap calculated per clock cycle - Already have higher clock rate available Two’s complement or SPT 24 bit Two’s complement 24 bit Two’s complement

29 Component Responses – Continuous Coefficients FIR1 FIR2 Sinc 2

30 Full Response with Continuous Coefficients

31 Full Response with SPT Coefficients

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33 Gentler Frequency Response Requires higher sampling rate

34 Summary  Audio ADC and DAC is a rich example of real world signal processing  System / Architectural Level Design Use digital technology to overcome weaknesses in analog  Filter Architectural Design CIC vs FIR vs IIR  Filter Optimization Structure Word lengths of coefficients and data

35 Presented By: David Hossack Analog Devices, Inc. 804 Woburn Street Wilmington MA