Noise Canceling in 1-D Data: Presentation #4 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Feb 14 th, 2005 Gate Level Design Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan: –Structural Verilog (Done) –Revised Floorplan (Done) To be done: –Schematics (85%) –Layout (5%) –Spice simulation

Previous Block Diagram

Final Block Diagram

Structural Verilog Output Behavioral Verilog Output Structural Verilog Output Similar Output Values. Differences due to 16-bit Floating Point Units

Result Comparison

New Transistor Count… Part Last Week’s Transistors New Transistors 16-bit FPA5x1700 = 85003x 4154 = bit FPM3x2028 = 60843x 3858 = Registers10x16x14 = 22407x16x14 = 1568 ROM800 Converter2x312 = 624 MUX/DEMUX384 Adder248 Counter214 Alternator64 Total ≈ Misc ≈ ≈ Misc ≈ 30000

Area Estimates PartLast week’s Area (µ²)New Area (µ²) 16-bit FPA5x140x110 = x140x140 = bit FPM3x140x106 = x170x170 = bit Register10x33x24 = 79207x33x24 = 5544 ROM43x180 = 7740 MUX/DEMUX6x6.8x57 = Converter2x20x40 = 1600 Counter Adder28x35 = 980 Alternator1x48 = 48 Total ≈ µ² + Misc ≈ µ² ≈ µ² + Misc ≈ µ²

Revised Floorplan

Mux 16-bit 2:1 Layout

Schematics

ROM

Alignment Shifter

Leading Zero Counter

Rounding Unit

Normalizing Unit

Wallace Tree Multiplier

Input of ROM Table Testbench

Test Results for Sine Time = 40ns Input: 2.52 (21 st value) SinOutput: =

Test Results for Cosine Time = 40ns Input: (21 st value) CosOutput: =

Critical Path Estimation Cycle 2 will be longer than Cycle 1 because it uses 3 FPM + 2 FPA while Cycle 1 uses 2 FPM + 3 FPA

Last week’s challenges… Finalizing out designs for the floating point adders and multipliers –Wallace tree multiplier vs Array multiplier Choose Wallace implementation because it saves 10% of power –Leading zero counter for normalizing block Found a smaller implementation of the normalizing block

This week’s challenges… Completing and Testing Top level Schematic Creating Layouts for Floating Point Multipliers and Adders with different shapes Clock Skew and other Timing issues Transistor count .. again..

Questions?