[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Sep 24 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates/  floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Traffic Flows Sensors (Blue) To detect the car entered Sensors (Red) To detect the car leaved ARM 1 ARM 2

Traffic Light Flow Whenever pedestrian push the button, then this light will insert in the end of this cycle. ARM 1 ARM 2 Red GreenY Green (S traight + R ight )YRed+Green(L eft ) Red Y Green (S traight + R ight )YRed+Green(L eft )Y Phase A Phase C Phase BPhase APhase B ARM1 ARM2 PED We define three phases (A,B,C) for different operations.

SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW (1bit) ARM (1bit) PED(1bit) CLK ARM1 [1:0] FSM Initial G.R Y.R R+L eft.R Y.R R.G R.Y R.R+L eft PED SW = 0 SW = 1 T < 2 T = 2 SW = 1 SW =0 T<10 PED = 1 T = 2 PED = 1 T = 2 T<= 2 SW = 0 T=15 T = 2 PED = 0 T = 2 PED = 0 ARM = 0ARM = 1 FSM For Lights Clear (1bit) ARM2 [1:0] PED(1bits) Blink T=10 T < 5 Complete(1bits)

Hold until n 1 or n 2 changes Light favors n 1 or n 2 ? n1n1 n2n2 T<r 1 ? T<r 2 ? T>= R 1 ?T>= R 2 ? n 1 =0? n 2 =0? f 1 <=0? f 2 <=0? Switch Light Reset T = 0 No Yes No Yes No Light favors arm 1 or arm 2 ? n1n1 n2n2 T<r left ? T>= R left ? No Yes No Yes No n 1 not change in T = 5? No Control reset Pedestrian For Green light For Red + Left T>= R p ? Yes No For Pedestrian n 2 not change in T = 5? n 1, n 2 :# of cars T :Time spent in this phase R i, r i : Max. and Min. time for each phase f i : the control function f 1 = α 1 *n 1 + β 1 – n 2 f 2 = α 2 *n 2 + β 2 – n 1

Floating Point Representation  12 Bit Representation  1 bit – Sign ( 0: Positive 1: Negative)  4 bits – Excess - 7 exponent with radix 2  7 bits – Significand / Mantissa e.g. [ ] SignExcessSignificand

Division?  Do we need to do division?  No, its not really necessary and it would require less time, power and area if done otherwise.  Beta = [ (Sum of 10 n values)*5 ] / (10*Q_Max)  Beta = (Sum of 10 n values)*5*(1/10)*(1/Q_Max)  The difference is that when the maximum queue length is set by the user, the reciprocal of the maximum queue length has to be entered.  In Blackout cases, a default Q value can be entered.

FPU Progress  Addition in 12-bits?  Yes  Subtraction in 12-bits ?  Yes  Multiplication in 12 bits?  No , issues generally having the exponent increased by a factor of two, while the significand is correct.  32 bits?  Yes Its fully tested, a little bug with the conversion exists that will be dealt with  Division in 12 bits?  Don ’ t need it anymore  32 bits?  Yes. It is fully tested, its based off of other FPU operations, thus not that hard to implement if a 12 bit version is needed

Some Test Cases Add Subtract Multiply 12 Bit ALU 1101

32 Bit Multiplication Thank you Perl and Intel for easy Floating Point References.

32 Bit Division

SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW (1bit) ARM (1bit) PED(1bit) CLK ARM1 [1:0] FSM Initial G.R Y.R R+L eft.R Y.R R.G R.Y R.R+L eft PED SW = 0 SW = 1 T < 2 T = 2 SW = 1 SW =0 T<10 PED = 1 T = 2 PED = 1 T = 2 T<= 2 SW = 0 T=15 T = 2 PED = 0 T = 2 PED = 0 ARM = 0ARM = 1 FSM For Lights Clear (1bit) ARM2 [1:0] PED(1bits) Blink T=10 T < 5 Complete(1bits)

module sig_control (arm1, arm2, ped, complete, arm, SW, PEDESTRIAN, clear, clk); output reg [1:0] arm1, arm2; output reg ped, complete; // 2-bit output for 4 states of signal, G, Y, R, Left; input arm; input SW, PEDESTRIAN; input clk, clear; reg [7:0] Y2RDELAY = 8'd2; // define delay for yellow to red reg [7:0] PEDDELAY = 8'd10;// define delay for pedestrain reg [7:0] PEDBLINK = 8'd5; // define delay for blinking parameter RED = 2'd0, YELLOW = 2'd1, GREEN = 2'd2, LEFT = 2'd3, PED_OFF = 1'd0, PED_ON = 1'd1; //state definition arm1 arm2 parameter S0 = 4'd0, //initial S1 = 4'd1, // G R S2 = 4'd2, // Y R S3 = 4'd3, // R+left R S4 = 4'd4, // Y R S5 = 4'd5, // R G S6 = 4'd6, // R Y S7 = 4'd7, // R R+left S8 = 4'd8, // R Y S9 = 4'd9, // Ped S10= 4'd10; // Ped Blinking reg [3:0] state; reg [3:0] next_state; clk, posedge clear) begin if(clear) state <= S0; else state <= next_state; end begin case(state) S0: begin arm1 = RED; arm2 = RED; ped = PED_OFF; complete = 1'b0; end S1: begin arm1 = GREEN; arm2 = RED; complete = 1'b0; end S2: arm1 = YELLOW; S3: begin arm1 = LEFT; complete = 1'b0; end S4: arm1 = YELLOW; S5: begin arm1 = RED; arm2 = GREEN; complete = 1'b0; end S6: arm2 = YELLOW; S7: begin arm2 = LEFT; complete = 1'b0; end S8: arm2 = YELLOW; S9: begin arm1 = RED; arm2 = RED; ped = PED_ON; complete = 1'b0; end S10:begin arm1 = RED; Verilog Behavior Modeling - Light Switching FSM (Cont.)

else next_state = S5; S6: begin clk); next_state = S7; complete = 1'b1; end S7: if(SW) next_state = S8; else next_state = S7; S8: begin clk); if(PEDESTRIAN) begin next_state = S9; complete = 1'b1; end else begin next_state = S1; complete = 1'b1; end S9: begin clk); next_state = S10; end S10:begin clk); next_state = S0; complete = 1'b1; end default: next_state = S0; endcase end endmodule ` Verilog Behavior Modeling - Light Switching FSM arm2 = RED; repeat(PEDBLINK) begin ped clk) ~ped; end endcase end or SW) begin case (state) S0: if(arm) next_state = S5; else next_state = S1; S1: if(SW) next_state = S2; else next_state = S1; S2: begin clk); next_state = S3; complete = 1'b1; end S3: if(SW) next_state = S4; else next_state = S3; S4: begin clk); if(PEDESTRIAN) begin next_state = S9; complete = 1'b1; end else begin next_state = S5; complete = 1'b1; end S5: if(SW) next_state = S6;

Design Decisions  Removal of Division Operation