ASIC1 progress Jamie Crooks, Feb 08. Bonding Problems: Resolved Smaller bonding wedge + revised programShorts to seal ring discovered under bonds.

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Presentation transcript:

ASIC1 progress Jamie Crooks, Feb 08

Bonding Problems: Resolved Smaller bonding wedge + revised programShorts to seal ring discovered under bonds

Bonding Status 18th August DPWRAL TD (optics lab)Threshold scan ok (some bumps, not completely normal) 919th November DPWRAL TD (optics lab) reworked with new bond program: shorts on pix/aco/dco power nets 11 19th November DPWICreworked with new bond program: threshold scan ok 15 19th November DPWRAL TD (optics lab) reworked with new bond program: (shapers bad; samplers good) 16 19th November DPWRAL TD (optics lab)reworked with new bond program: threshold scan ok 17 19th November DPWRAL TD (optics lab)reworked with new bond program: threshold scan ok 19 19th November DPWRAL TD (optics lab) reworked with new bond program: threshold scan fails (no RE signals?) 22/1 18/1 29/1 1/2 22/1 Bonded # Status Wafer/Split Location Notes

(per diode) PreSample Test Pixel Pixel node (ideal simulation) Test Pad (ideal simulation) PCB Sat. Limit (measured) Diode node (ideal simulation) Test Pad (measured) (diode voltage step is applied through Vrst, signal step at pad is measured & plotted such that it corresponds to the diode node voltage step in the simulation) Test Pad Sat. Limit (measured) (14fF parasitic on diode node) Fe55

System overview: preSample test pixels Charge Gain (Diode)Voltage Gain (Electronics) Q V diode V pix V pad Voltage Gain (Buffers) = 5.7 uV/e- (sim) (Can be estimated from ) Gain ~0.8 from simulations Can be measured by applying Vstep to Vrst holding pixels in reset Can be simulated by placing a voltage pulse on the diode node Fe55 measurement should give calibration of this gain Can be simulated using ideal or parasitic extracted pixel models and injecting charge

Voltage gain Simulations place an ideal voltage step on the diode node therefore independent of Cdiode Measurements apply a voltage step on the diode node through the VRST transistor, therefore independent of Cdiode 62 V/V 24 V/V 31 V/V Fe55

Compare with previous data Assuming 5.7 uV/e- conversion Vrst step

Measured voltage gain on 4 sensors

System overview: preSample test pixels Charge Gain (Diode)Voltage Gain (Electronics) Q V diode V pix V pad Voltage Gain (Buffers) These figures combined have been generally quoted before during design phase, in uV/e- Any measurements taken with the test pixels will include the two buffer stages with gain<1 From Fe55 measurements = 130uV/e- Est. from Fe55 meas. = 161uV/e- = 5.7 uV/e- (sim) = 31 V/V (est. from meas)= 0.8 V/V (sim) = 24 V/V (measured) (136uV/e-)

Noise Assumptions –We are in the linear region of test pixel –Parasitic capacitance estimate of diode node is ~correct System gain –from diode to pad Noise –measured by Marcel at pad –referred back to diode using gain –Will be sampled in-pixel during normal operation SNR –Typical signal –Worst case signal in corner = 130uV/e- = 3.5mV 207mV 1600e- = 27 e- 3.5mV 130uV/e 27 * √2 = 38 e- 250e- = 6.5

Linearity Measurements Laser intensity (%) Signal (mV) Giulio’s laser calibration Aug 07 Pixel saturation Laser non-linearity Series1 Sensor 1: 12um epi +DPW; (PCB modified for AC coupling) Series2 Sensor 16: 5um epi +DPW (standard PCB design)

Linearity Sweeps 11x11 shutter 6x6 shutter 16x16 shutter Non-linear region of laser

(Data from Jamie B) samplers with source samplers without source shapers with source shapers without source histogram of the number of hits at each timestamp integrated over a very large number of bunch trains (~360k), for thresholds down to 160.