Quad 2-to-1 Multiplexer Discussion D7.4 Example 7.

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Quad 2-to-1 Multiplexer Discussion D7.4 Example 7

Quad 2-to-1 Multiplexer

assign y = ~s & a | s & b;

{0,0,0,~s} & {a[3],a[2],a[1],a[0]} = {0,0,0,~s & A[0]} ~s & a; {4(~s)} & A = {~s,~s,~s,~s} & {a[3],a[2],a[1],a[0]} = {~s & a[3],~s & a[2],~s & a[1],~s & a[0]}

// Example 7a: Quad 2-to-1 mux using logic equations module mux24( input wire [3:0] a, input wire [3:0] b, input wire s, output wire [3:0] y ); assign y = {4{~s}} & a | {4{s}} & b; endmodule

// Example 7b: Quad 2-to-1 mux using if statement module mux24( input wire [3:0] a, input wire [3:0] b, input wire s, output reg [3:0] y ); if(s == 0) y = a; else y = b; endmodule

// Example 7c: Quad 2-to-1 mux using ? operator module mux24( input wire [3:0] a, input wire [3:0] b, input wire s, output wire [3:0] y ); assign y = s ? b : a; endmodule

Aldec Active-HDL Simulation