1 Instructions and Addressing

TU-Delft TI1400/11-PDS 22 Lecture 1 Making functions time A,B Y  A B Y ADD nand gates

TU-Delft TI1400/11-PDS 3 Lecture 1 Making functions Circuit Diagram

TU-Delft TI1400/11-PDS 4 Lecture 2 Programmable device 2,1 3 Programmable Device input stream output stream program READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) READ(X) means read next input value from input stream and store it internally as variable X WRITE(X) means put value in variable X on output stream ADD(X,Y,Z) means assign value of X+Y to Z

TU-Delft TI1400/11-PDS 5 Lecture 3 Von Neumann Architecture READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) X: 1 Y: 2 Z: 3 TEMP_A: TEMP_B: RESULT: IR: PC: arithmetic unit Central Processing Unit CONTROL Memory Input Output

TU-Delft TI1400/11-PDS 6 Problem: How to Represent and Use Data? 1.Representation 2.Arithmetic 3.Conversion

TU-Delft TI1400/11-PDS 7 Lecture 2 Von Neumann Architecture READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) X: 1 Y: 2 Z: 3 TEMP_A: TEMP_B: RESULT: IR: PC: arithmetic unit Central Processing Unit CONTROL Memory Input Output

TU-Delft TI1400/11-PDS 8 Problem: How to Represent and Use Data Instructions? 1.Representation 2.Use (Addressing Data)

TU-Delft TI1400/11-PDS 99 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing

TU-Delft TI1400/11-PDS 10 Computer System READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) X: 1 Y: 2 Z: 3 IR: PC: arithmetic unit Central Processing Unit control unit Main Memory Input Output registers Data and Instructions Instruction RegisterProgram Counter

TU-Delft TI1400/11-PDS 11 Main Memory Addressing Bit Byte (8 bits) Word (16-64 bits) Address 0 Address

TU-Delft TI1400/11-PDS 12 Q1: How many bits required to address? 1.1KB of memory A.By Bit (13) B.By Byte (10) C.By Word of 32 bits (8) 2.1MB of memory A.By Bit (23) B.By Byte (20) C.By Word of 32 bits (18) 3.1GB of memory A.By Bit B.By Byte C.By Word of 32 bits 4.1TB of memory A.By Bit B.By Byte C.By Word of 32 bits Q2: How much memory can be addressed by byte for a 32-bit architecture? Q3: Why use byte memory addressing?

TU-Delft TI1400/11-PDS 13 Instruction and wordlength (1/3) instruction word instruction instruction word address

TU-Delft TI1400/11-PDS 14 Instruction and wordlength (2) instruction instruction word address instruction instruction

TU-Delft TI1400/11-PDS 15 Instruction and wordlength (3) word address instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr

TU-Delft TI1400/11-PDS bit word formats opcode specifier operand specifiers byte byte byte byte a two’s complement number 4 ASCII characters 32 bit a machine instruction

TU-Delft TI1400/11-PDS 17 Byte ordering (endianness) Word Index Big endian e.g., Motorola PowerPC 68k Little endian e.g., Intel Jonathan Swift’s Gulliver’s Travells

TU-Delft TI1400/11-PDS 18 Q1 (the NUXI problem) What problems can occur in porting data between machines with big-endian and little-endian storage? (Hint: networked machines) Q2 Why use the little endian byte ordering? Q3 Why use the big endian byte ordering? (Hint: value 4 as single- and multi-byte)

TU-Delft TI1400/11-PDS 19 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing 2.1. Data Copy Operations 2.2. Arithmetic And Logic Ops Program flow control Ops I/O operations

TU-Delft TI1400/11-PDS 20 Types of Instructions There are 4 types of instructions -Data Copy operations between memory and registers between memory locations between registers -Arithmetic and Logic operations -Program flow control operations -I/O operations

TU-Delft TI1400/11-PDS 21 Symbolic notation Copy instructions [R 1 ]  M(LOC) Arithmetic operations M(C )  M(A ) + M(B) LOC, A, and B are memory addresses M(address) means contents of memory location at address. [R] means contents of register R.

TU-Delft TI1400/11-PDS 22 Operand specification formats Three-address instructions format: INSTR source#1,source#2,destination example: Add A,B,C means: M(C )  M(B) + M(A) Problem: 3-address instructions means long instruction words. -If k bits are needed for memory addressing, then 3k bits are needed for addressing operands. (k=32 for 32-bit platforms.)

TU-Delft TI1400/11-PDS 23 Operand specification formats Two address instructions format: INSTR source, destination example: Add A,B means: M(B)  M(B) + M(A) Problem: 2-address instructions mean somewhat long word or multiple FETCHes per instruction. -If k bits are needed for memory addressing, then 2k bits for addressing operands. (k=32 for 32-bit platforms.)

TU-Delft TI1400/11-PDS 24 Two address instruction Additional Problem: Operand Override Add A,B Two operand instructions destroy contents of the B location Need other instruction to avoid that: Move B,C We then have Move B,C Add A,C meaning: M(C)  M(B) ; M(C)  M(C) + M(A) ;

TU-Delft TI1400/11-PDS 25 One address instructions One address -have implicit source (often called Accumulator) Load A Add B Store C meaning [Accu ]  M(A) ; [Accu ]  [Accu ] + M(B) ; M(C)  [Accu ]

TU-Delft TI1400/11-PDS 26 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing

TU-Delft TI1400/11-PDS 27 Registers Many computers have a number of General- Purpose registers inside the CPU Access to registers is faster than to memory locations Used to store temporary data during processing Registers require less bits of address than main memory

TU-Delft TI1400/11-PDS 28 Register addressing Let Ri denote register General operation ADD A,B,C can be broken down to Move A,R0 Add B,R0 Store R0,C meaning [R0]  M(A) ; [R0]  [R0] + M(B) ; M(C)  [R0]

TU-Delft TI1400/11-PDS 29 Instruction Formats (Summary) opcode specifier operand specifiers general format one operand addressing opcode operand operand two operand addressing opcode operand

TU-Delft TI1400/11-PDS 30 Accumulator architecture Accumulator PC CPU Main Memory

31 Question How many instructions can be defined when the opcode field is 5 bit ?

TU-Delft TI1400/11-PDS 32 Example instruction accu 4 bits 12 bits opcode operand m 15 0 sign bit

TU-Delft TI1400/11-PDS 33 Instruction set

TU-Delft TI1400/11-PDS 34 Multiple register architecture R0 CPU Main Memory R1 R2 R3

TU-Delft TI1400/11-PDS 35 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing

TU-Delft TI1400/11-PDS 36 Straight-line sequencing …... ……. Move A,R0 Add B,R0 Move R0,C i i+4 i+8 A B C address Program for M(C)=M(B)+M(A)

TU-Delft TI1400/11-PDS 37 Straight-line sequencing Add Nn,R0 Move R0,S Move N1,R0 Add N2,R0 Add N3,R0 i i+4 i+8 i+4n-4 i+4n address Program for addition of n numbers

TU-Delft TI1400/11-PDS 38 Branching n Clear R0 Move N,R1 Decr R1 Branch>0 L Move R0,S L S N N1 Nn Program for addition of n numbers Determine address of “next” number and add it to R0 program loop

TU-Delft TI1400/11-PDS 39 Common branch conditions N (negative) set to 1 of result is negative Z (zero) set to 1 of result is zero V (overflow) set to 1 of result overflows C (carry) set to 1 of carry-out results

40 Question Why is the carry condition important?

TU-Delft TI1400/11-PDS 41 Instructions and Addressing 1.Memory Layout 2.Types of Instructions 3.Use of Accumulator/Registers 4.Execution of Instructions 5.Addressing 5.1. Addressing Modes 5.2. Immediate Addressing 5.3. Direct Addressing 5.4. Indirect Addressing 5.5. Index Addressing

TU-Delft TI1400/11-PDS 42 Addressing modes Addressing modes determine how the address of operands is determined Typical 4 addressing modes -immediate addressing -direct addressing -indirect addressing -index addressing

TU-Delft TI1400/11-PDS 43 Immediate addressing (1) opcode specifier operand instruction ADD # -1 JNZ example: simple counting loop

TU-Delft TI1400/11-PDS 44 Immediate addressing (2) Advantages: -no additional calculations needed to obtain operand -fast Disadvantages: -Operand value must be known -Operand value cannot be changed -Limited no of bits available Notation: MOVE #200,R0 Meaning: [ R0 ]  200

TU-Delft TI1400/11-PDS 45 Direct addressing(1) opcode specifier mem or reg address instruction memory or registers ADD 13 JNZ 10 #

TU-Delft TI1400/11-PDS 46 Direct addressing(2) Advantages: -Operand separate from instruction -Can be changed -Full word length available Disadvantages: -More memory accesses -More storage occupation Notation: ADD R1,R2 Meaning: [ R2 ]  [ R2 ] +[ R1 ] Also called “Absolute addressing” (Ham.)

TU-Delft TI1400/11-PDS 47 Indirect addressing (1) ADD (12) JNZ # opcode specifier mem or reg address instruction op. address operand memory or registers

TU-Delft TI1400/11-PDS 48 Indirect addressing (2) Advantages: -Actual address of operand is not in instruction -Can be changed Disadvantages: -Even more memory or register references -More memory occupation Notation: ADD (R1),R2 Meaning: [ R2 ]  [ R2 ] + M( [ R1 ])

TU-Delft TI1400/11-PDS 49 Example indirect addressing program loop L N N1 Clear R0 Move N,R1 Move #N1,R2 Add (R2),R0 Add #4,R2 Decr R1 Branch>0 L Move R0,S n S

TU-Delft TI1400/11-PDS 50 Index addressing (1) opcode Reg index instruction operand memory or registers operand + registers

TU-Delft TI1400/11-PDS 51 Index addressing (2) Advantages: -Allows specification of fixed offset to operand address Disadvantages: -Extra addition to operand address Notation: ADD X(R1),R3 (X=number) Meaning: [ R3 ]  [ R3 ] + M( [ R1 ] + X )

TU-Delft TI1400/11-PDS 52 Example index addressing NENE Program with index addressing program loop sex age salary n Empoyee ID sex age salary Empoyee ID L Move #E,R0 Move N,R1 Clear R2 Add 8(R0),R2 Add #16,R0 Decrement R1 Branch>0 L Div R1,R2 Move R2,Sum Move N,R1

TU-Delft TI1400/11-PDS 53 Additional modes Some computers have auto-increment (decrement instructions) Example: (R0)+ Meaning.. M(R0 )..; [ R0 ]  [ R0 ]+1 Example: - (R0) Meaning [ R0 ]  [ R0 ]-1;.. M(R0 )..