Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Basic Component Layout 02/18/2004 Current Stage: Basic Component Layout 02/18/2004 Design Manager: Rebecca Miller

Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Full-chip Transistor-level Schematic (100% done)  Component Layout Another new Floor Plan Another new Floor Plan Basic components (100% done) Basic components (100% done)  To be done Spice Simulation Spice Simulation Layout of larger blocks (90% done) Layout of larger blocks (90% done) Some permutations layouts Some permutations layouts Top-Level layout routing Top-Level layout routing

Revised Architecture KeyReg 56’b Register 32’b 32’b input Enc_ShiftL Dec_ShiftR IP -1 wiring PC-2 Wiring 56->48 IP wiring Text 64’b Register Expand 32->48 wiring S-Box 512 x 4’b P 32->32 wiring PC (wiring) 32’b Latch 2:1 mux Sub_rnd e/d txt_in ready key_in Sh_d Sh_e “R” “L” R L wr_en OUT ready 32 2:1 mux :1mux 32’b Latch

Top Level “des3”

Updated Floorplan 32’b Latch PC1 Mux 56’b Key Reg PC2 IP Mux IP-1 32’b Text Register (L) 32’b Text Register (R) 32’b Mux 32’b XOR Expand 48’b XOR P SBOX Right Shift Left Shift Right Shift Left Shift 32’b Mux All large functional blocks use Metal 1 and Metal 2. M1 M2 M3 M4 Input Mux Output Program Control clock 416μm 360μm

Pin Connections / Porosity

Project Goals Implement fully functioning 3DES Chip Implement fully functioning 3DES Chip Speeds high enough for credit card transactions Speeds high enough for credit card transactions Dense design for small area Dense design for small area

Inverter / Buffer

Exclusive OR

D Latch

2:1 Multiplexor

D Flip Flops Enable / Reset asserted high No Enable / Reset asserted high

Half Adder

Left Barrel Shifter

Right Barrel Shifter

Program Control

56’b Key Register

32’b Latch

32’b Exclusive OR

32’b 2:1 Multiplexor

PC1 Permutation

64’b Text Register

SBOX1 ROM

Updated Transistor Counts and Area

Area mm 2 Transistors15,238 Density0.08 trans/μm 2

Design Decisions  Stick with hardwiring for permutations  Inputs and outputs on same side  Layed out in one long row of skinny modules

Questions ?