1 Lecture 5: IC Fabrication The Transistor Revolution First transistor Bell Labs, 1948 © Rabaey: Digital Integrated Circuits 2nd

2 Lecture 5: IC Fabrication The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 © Rabaey: Digital Integrated Circuits 2nd

3 Lecture 5: IC Fabrication Intel 4004 Micro-Processor transistors 1 MHz operation © Rabaey: Digital Integrated Circuits 2nd

4 Lecture 5: IC Fabrication Moore’s Law Electronics, April 19, © Rabaey: Digital Integrated Circuits 2nd

5 Lecture 5: IC Fabrication Silicon IC processing F Similar to photographic printing íExpose the silicon wafer through a mask íProcess the silicon wafer íRepeat sequentially to pattern all the layers F Layout: A set of masks that tell a fabricator what to pattern íFor each layer in your circuit íLayers are metal, drain/source implants, gate, etc. íYou draw the layers ç Subject to vendor-supplied spacing rules

6 Lecture 5: IC Fabrication The wafer F Czochralski process íMelt silicon at 1425 °C íAdd impurities (dopants) íSpin and pull crystal F Slice into wafers í0.25mm to 1.0mm thick F Polish one side

7 Lecture 5: IC Fabrication

8 Crystal and wafer Wand (a finished 250lb crystal) A polished wafer

9 Lecture 5: IC Fabrication 4X reticle Wafer The mask F Illuminate reticle on wafer íTypically 4× reduction F Typical image is 25×25mm íLimited by focus F Step-and repeat across wafer íLimited by mechanical alignment

10 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS Lithography F Patterning is done by exposing photoresist with light F Requires many steps per “layer” F Example: Implant layer

11 Lecture 5: IC Fabrication Grow Oxide Layer Reference: FULLMAN KINETICS

12 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS Add Photoresist

13 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS Mask

14 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS Animation

15 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

16 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

17 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

18 Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

19 Lecture 5: IC Fabrication 9/03 IEEE spectrum

20 Lecture 5: IC Fabrication Patterning F How we pattern and expose the resist íTo make the patterns we want on the silicon IEEE Spectrum, 7/99, p. 41

21 Lecture 5: IC Fabrication 9/03 IEEE spectrum

22 Lecture 5: IC Fabrication Detailed process sequence 1.Grow epi layer íUltra-pure single-crystal silicon 2.Implant n-well

23 Lecture 5: IC Fabrication Detailed process sequence (con’t) 3.Define active area 4.Grow field oxide íFor isolation

24 Lecture 5: IC Fabrication Detailed process sequence (con’t) 5.Grow gate oxide 6.Pattern polysilicon

25 Lecture 5: IC Fabrication Detailed process sequence (con’t) 7.Form pFETs 8.Form nFETs

26 Lecture 5: IC Fabrication Detailed process sequence (con’t) 9.Deposit LTO by CVD íLTO is low-temperature oxide íCVD is chemical vapor deposition 10. Deposit Metal1 íUsually aluminum

27 Lecture 5: IC Fabrication Detailed process sequence (con’t) 11. Via definition íDeposit LTO íMake via cuts 12. Deposit Metal2 íUsually aluminum 13. Overglass (not shown) íCoat entire chip with Si 3 N 4 íMake pad openings in Si 3 N 4

28 Lecture 5: IC Fabrication An inverter

29 Lecture 5: IC Fabrication Figure courtesy Yan Borodovsky, Intel A Pentium cutaway

30 Lecture 5: IC Fabrication National 0.18µm process cutaway

31 Lecture 5: IC Fabrication Advanced Metallization - Copper Copper versus Aluminum ~ 40% lower resistivity ~ 10× less electromigration

32 Lecture 5: IC Fabrication Interconnect Impact on Chip

33 Lecture 5: IC Fabrication Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

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35 Lecture 5: IC Fabrication Permittivity

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40 Lecture 5: IC Fabrication Projections Simulated distribution of dopant atoms in a 0.05  m nFET red: acceptor atom blue: donor atom All figures from IEEE Spectrum, 7/99

41 Lecture 5: IC Fabrication An AMD 50nm transistor

42 Lecture 5: IC Fabrication Frequency P6 Pentium ® proc Year Frequency (Mhz) Lead Microprocessors frequency doubles every 2 years Doubles every 2 years Courtesy, Intel © Rabaey: Digital Integrated Circuits 2nd

43 Lecture 5: IC Fabrication Power Dissipation P6 Pentium ® proc Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel © Rabaey: Digital Integrated Circuits 2nd

44 Lecture 5: IC Fabrication Power density Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel © Rabaey: Digital Integrated Circuits 2nd

45 Lecture 5: IC Fabrication Productivity Trends ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity Courtesy, ITRS Roadmap © Rabaey: Digital Integrated Circuits 2nd

46 Lecture 5: IC Fabrication Cost of Integrated Circuits F NRE (non-recurrent engineering) costs ídesign time and effort, mask generation íone-time cost factor F Recurrent costs ísilicon processing, packaging, test íproportional to volume íproportional to chip area

47 Lecture 5: IC Fabrication NRE Cost is Increasing © Rabaey: Digital Integrated Circuits 2nd

48 Lecture 5: IC Fabrication Die Cost Single die Wafer From Going up to 12” (30cm) © Rabaey: Digital Integrated Circuits 2nd