W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California The CMOS Inverter: Current Flow during Switching V IN V OUT V DD 0 0 N: off P: lin N: lin P: off N: lin P: sat N: sat P: lin N: sat P: sat A BDE Ci i S D G G S D V DD V OUT V IN

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Power Dissipation due to Direct-Path Current V DD -V T VTVT time v IN : i:i: I peak V DD 0 0 i S D G G S D V DD v OUT v IN Energy consumed per switching period: t sc

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California An NMOSFET is a closed switch when the input is high N-Channel MOSFET Operation NMOSFETs pass a “strong” 0 but a “weak” 1 Y = X if A and B Y = X if A or B B A X B A X YY

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California A PMOSFET is a closed switch when the input is low P-Channel MOSFET Operation PMOSFETs pass a “strong” 1 but a “weak” 0 Y = X if A and B = (A + B) Y = X if A or B = (AB) B A X B A X YY

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Pull-Down and Pull-Up Devices In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to V DD. –An NMOSFET functions as a pull-down device when it is turned on (gate voltage = V DD ) –A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) F(A 1, A 2, …, A N ) PMOSFETs only NMOSFETs only … … Pull-up network Pull-down network V DD A1A2ANA1A2AN A1A2ANA1A2AN input signals

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California CMOS NAND Gate ABF A F B AB V DD

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California CMOS NOR Gate A F B A B V DD ABF

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California CMOS Pass Gate A X Y A Y = X if A

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Logic Gates – From Week 9b A B F=A·B AND F = A B NAND NOR A B NOT A OR A B F=A+B EXCLUSIVE OR A B F =

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Logic Gates – How are they used? A B C=A·B AND First of all we must agree on what is high (logical 1) or low (logical 0). Suppose 1.5 V is 1 and 0V is logical 0. C would have the value of 1.5 V (logical 1). But it would have the value of 0V (logical 0) if either one of the inputs were held at zero V. AND 1.5V

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California What are the most basic gates in Digital Electronics? ABAB Not-AND = NAND A B AB A+B BA  Not-OR = NOR A B Typically use one or the other: “NAND logic” or “NOR logic”

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California How to Combine Gate to Produce a Desired Logic Function? (This is called Logical Synthesis) Not-AND = NAND A B A B NOT AND Logically just an AND plus a NOT gate: Example A B AND Shorthand for NOT

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California How to Combine Gate to Produce a Desired Logic Function? (More basic Logical Synthesis) A Example F= A B. B A B A B. Again a little shorthand is useful

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California How to Combine Gate to Produce a Desired Logic Function? (More basic Logical Synthesis) Suppose we are given a truth table (all logic statements can be represented by a truth table). How can we implement the function? Answer: There are lots of ways, but one simple way is implementation from “sum of products” formulation. How to do this: 1) Write sum of products expression from truth table and 2) Implement using standard gates. (Warning this is probably inefficient – we need to minimize, or simplify the expression)

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California How to Combine Gate to Produce a Desired Logic Function? (More basic Logical Synthesis) Example: ABCF or Clearly: F= 1 if C = 1 AB =1 i.e. F= C +AB

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California How to Combine Gate to Produce a Desired Logic Function? (More basic Logical Synthesis) Example: ABCF F= C +AB A B C A B C F

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California More Logical Synthesis Example: ABF F=A +AB A B A B F Clearly Thus But it is easy to show that a simpler valid expression for F is F = B, hence: B F (ignore A)

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California What circuit of logic gates could produce these (arbitrarily chosen) outputs F in response to inputs A, B and C? ABCF ABCF

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Rules of boolean algebra. The two entries in the last row are used frequently and are known as DeMorgan’s theorem. AND RulesOR Rules AA=A A+A=A AA=0 A+A=1 0A=0 0+A=A 1A=A 1+A=1 AB=BA A+B=B+A A(BC)=(AB)C A+(B+C) = (A+B)+C A(B+C) =AB+AC A+BC=(A+B)(A+C) AB=A+B A+B=AB

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Logical Synthesis Guided by DeMorgan’s Theorem Demorgan’s Theorem : or Thus, for example: A B C D F Thus any sum of products expression can be immediately synthesized from NAND gates alone

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California Karnaugh Maps Graphical approach to minimizing the number of terms in a logic expression: 1.Map the truth table into a Karnaugh map (see below) 2.For each 1, circle the biggest block that includes that 1 3.Write the product that corresponds to that block. 4.Sum all of the products A B 2-variable Karnaugh Map A 1 0 BC variable Karnaugh Map 4-variable Karnaugh Map CD AB

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California ABCS1S1 S0S InputOutput A BC AC AB S 1 = AB + BC + AC Simplification of expression for S 1 : Karnaugh Map Example By simplifying we can reduce the number of gates, transistors, and the size of the circuits.