ELEN 468 Lecture 211 ELEN 468 Advanced Logic Design Lecture 21 HDL Coding Styles

ELEN 468 Lecture 212 Coding Guidelines Readable Maintainable Reusable

ELEN 468 Lecture 213 Directory Using a common directory structure makes it easy to locate designs Example project directory: bin/project-wide scripts/commands doc/project-level documentation beh/behavioral models rtl/ structural rtl model syn/synthesis scripts & logs phy/physical models and SDF data verif/verif suite and simulation logs

ELEN 468 Lecture 214 Comments Header is always necessary: // main.v // (c) Copyright 2002, Texas A&M University // All rights reserved. // // This file contains proprietary and confidential // information. The content or any derivative // work can only be used by or distributed to // licensed users or owners. // // Description: Demo program for ELEN 468 // // Original author: John Q. Doe // // History: See bottom of the file.

ELEN 468 Lecture 215 Comments Target audience: junior engineers who know the language, but not familiar with the design and must maintain and modify design Describe the function, not the action Useless comments:  k = k + 1; // increment k Useful comments:  k = k + 1; // move pointer to next input bit If you feel you need to explain but can’t find proper words, think.

ELEN 468 Lecture 216 Comments For each module, function and task, describe its function, input/output variables Declaration Layout // poor integer cta, ctb; real ctime; reg [0:31] sum; // good integer cta;// counter for a integer ctb;// counter for b reg [0:31] sum; real ctime; // counting time, for simulation

ELEN 468 Lecture 217 Layout One statement per line No more than 80 characters per line Break long lines Align the line properly #10 bad = something + somethingelse + leftover; #10 good = something + somethingelse + leftover;

ELEN 468 Lecture 218 Indentation Use a minimum of 3 spaces and maximum of 8 spaces for each indentation level. Avoid excess indent due to if-else, begin-end begin if (x == 1’b0) begin y <= x; end else y <= ~x; end endmodule begin if (x == 1’b0) begin y <= x; end else y <= ~x; end endmodule

ELEN 468 Lecture 219 Port Association Name association is more robust than port order mymodule m1(u, v, w, x, y, z); mymodule m2 (.clock(u),.reset(v),.clear(w),.data_in(x),.ctrl_in(y),.sample(z));

ELEN 468 Lecture 2110 Structurally Simple Use no more than 3 levels of nesting Avoid nested loops  Convert nested loops to separate loops Use case instead of if-else  case {a,b,c}  if (a==1’b1) if (b==1’b1) if (c == … No more than 50 consecutive assignments in any block

ELEN 468 Lecture 2111 Name Guidelines Use lower case letters in all user defined identifiers Use upper case for constants Do not rely on case to distinguish uniqueness Separate words using underscore ReadNextInput v.s. read_next_input

ELEN 468 Lecture 2112 Case Do not rely on case to distinguish uniqueness. Easy to make mistake. // bad input ctrl; output Ctrl; // good input ctrl_in; output ctrl_out;

ELEN 468 Lecture 2113 Suffixes Use suffixes to semantically differentiate related variables Type, constant, signal, variable, flipflop, pipeline stage, function Example: ctrl_alu, ctrl_dm, ctrl_reg; Function/purpose is better than implementation Best: data_in, data_out OK: data_32, data_16

ELEN 468 Lecture 2114 Variables Avoid using reserved words in popular languages Have to rename if translated to another language Popular languages: C, C++, Verilog, VHDL, PERL Use meaningful names Poor names: if (e==1’b1) c<=c+1; Good names: if (enable==1’b1) counter<= counter + 1; Use i, j, k, l, m and n as integer variables

ELEN 468 Lecture 2115 Constants Use symbolic constants instead of hard- coded numerical values Bad: reg [255:0] data; Good: reg [WIDTH-1:0] data;

ELEN 468 Lecture 2116 Preserve Names Preserve names across hierarchical boundaries, if possible module traffic(light, pedx, clock); traffic t_univ(.light(light_univ),.pedx(pdex_univ),.clock(clock)); traffic t_texas(.light(light_texas),.pdex(pdex_texas),.clock(clock)); Tracing signals made easy

ELEN 468 Lecture 2117 Race Condition ( posedge clk )// c will get previous b or new b ? c = b; ( posedge clk ) b = a; ( posedge clk )// c will get previous b or new b ? c = b; ( posedge clk ) b = a;

ELEN 468 Lecture 2118 Avoid Race Condition ( posedge clk )// Solution 1: merge always begin c = b; b = a; end ( posedge clk )// Solution 2: intra-assignment delay c = #1 b; ( posedge clk ) b = #1 a; ( posedge clk )// Solution 3: non-blocking assignment c <= b; ( posedge clk ) b <= a; ( posedge clk )// Solution 1: merge always begin c = b; b = a; end ( posedge clk )// Solution 2: intra-assignment delay c = #1 b; ( posedge clk ) b = #1 a; ( posedge clk )// Solution 3: non-blocking assignment c <= b; ( posedge clk ) b <= a;

ELEN 468 Lecture 2119 A Nice Verilog Website