Project D1427: Stand Alone FPGA Programmer Characterization presentation 10/12/08 Supervisor: Mony Orbach Students: Shimrit Bar Oz Avi Zukerman High Speed Digital Systems Lab

Agenda Project target. Projects inputs and outputs. Function. Technical description. Studies. Schedule.

Project target Design a system for programming Altera FPGA directly from a PC (without Quartus). –A secondary option can be for the system to be able to program the FPGA with either the USB inputs or with JTAG inputs.

Project inputs and outputs Inputs: program to be loaded to a FPGA from a PC. Outputs: The same program in JTAG format USB formatJTAG formatController

Function The system gets gate level burn ready software from PC. Translate to JTAG format. Burn the software onto an Altera FPGA. Optional functionality is to enable direct JTAG burning using the same system.

Technical description The system is based on a logical unit. This card must have USB communication unit. The JTAG inputs will be used to program the logical unit and can also be used as JTAG inputs to the system. USB communication Unit logical unit USB inputsJTAG output JTAG inputs

Studies Before starting to work on the project following materials will be studied: –The Altera Cyclone FPGA. –JTAG protocol. –SOF protocol, and how to translate it to JTAG. –Quartos work environment. –Search for alternative cards suitable for this system.

Schedule 10/12/08 – Characterization presentation. 15/12/08 –JTAG and SOF protocols and synchronization. 22/12/08 – Ramp up work environment. Simple tests with Altera Cyclone FPGA. 29/12/08 – Midterm presentation.