DUSD(Labs) EE249 Project: Partitioning Algorithms & Modeling Methodologies for HW/SW Partitioning in Metropolis Mentor: John Moondanos, GSRC Visiting Fellow, UC Berkeley & Strategic CAD Labs Intel Corp.

2 Problem Statement u HW/SW partitioning deals with assigning parts of a system description to heterogeneous implementation units s Key task in system level design due to the downstream cost & performance consequences of the initial partitioning choices u Multi-faceted s Processor & flash on the same die or not? s Functionality Partitioning into chips s Hardware vs. Software functionality Implementation s Which functions to which type of silicon? u Difficult to model & analyze with conventional RTL Tools u Of course, the focus is on how it affects power consumption

3 Goal of the Project u Briefly Review the literature to capture the state of the art u Develop technologies and methodologies for solving the partitioning problem within the Metropolis environment s Methodologies will focus more on the system modeling methodology that is better suited for the capabilities of Metropolis s Technologies will focus more on the algorithms that must be used to accomplish the partitioning using the capabilities of the Metropolis environment.

4 Suggestion for Design Driver for this Project u For the hardware: The PXA800F cell phone processor from Intel s Some publicly available introductory material on the PXA800F is available in the “backup material section” s Modeling of the Xscale can happen with the GnuPro simulator u For the Software: We have available Statistical Models for typical applications that run on the PXA800F

5 Backup Material u Overview of the PXA800F cellular phone Processor u References

6 The Intel® PXA800F Cellular Processor u Full GSM/GPRS Class solution  High-performance/Low-power Intel® XScale ™ technology core, providing class-leading headroom for rich data applications  Intel® Micro Signal Architecture  Intel® On-Chip Flash Memory s GSM/GPRS Communications Stack, RTOS and applications code for a single-chip mobile solution

7 The Intel® XScale ™ in the PXA800F u High-performance, power-efficient processor supports data-intensive applications  Processor core operates at an adjustable clock frequency from 104 to 312 MHz  Instruction cache and Data cache memories  4 MB integrated Intel On-Chip Flash memory  512 KB integrated SRAM  Memory controller supports synchronous Flash mode, page mode Flash, SRAM, DRAM, and variable latency  DMA controller  Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC  Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP, Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick, Dallas* 1-Wire* Interface, keypad, PWM D/A, JTAG  Interfaces for Bluetooth, IrDA, GPS and digital camera peripherals  LCD Controller for up to 120 x 240 display 16-bit color or gray scale

8 Intel Micro Signal Architecture in the PXA800F u Performs GSM/GPRS baseband signal processing  Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz execution clock  Instruction cache and 64 KB dual-banked data SRAM u 512 KB integrated Intel On-Chip Flash for field-upgradable signal processing firmware  Includes microprocessor instructions such as bit manipulation u Includes cipher and Viterbi accelerators  Multiple sleep modes and integrated power management minimize power consumption  Interface support-digital I/Q, voice codec, auxiliary serial port for mixed- signal analog baseband, I2S audio codec interface, RF synthesizer serial control interface, JTAG

9 The Memory Subsystem  The Intel® XScale ™ s Instruction and Data Cache s 4MB of Flash & 512KB of SRAM always at 104MHz s Memory Controller managing accesses to external SRAM u The MSA s Integrated 64KB SRAM for microcontroller like instructions Special instructions for maximizing GSM/GPRS performance Special instructions for maximizing GSM/GPRS performance s 512KB of flash for program store

10 PXA800F Block Diagram UARTs for Bluetooth, IRDA GSM Sim card I/F External Power Management I/F Synch Serial Port Smart Battery I/F

11 PXA800F Block Diagram Memory Stick Programmable Clock Secure Card I/F Pulse Width Modulator for buzzer Timing Control Unit For basestation timing Encrypt/Decrypt GSM data offloading MSA

12 PXA800F Block Diagram Viterbi error decoding offloading MSA High Speed Logger For debug Full Bandwidth (Hi- Fi) digital audio I/F DSP Synchronous Serial Ports interfacing with RF, speech

13 PXA800F Block Diagram IF ES ED IS BIU Switch Peripheral Bus 1 Peripheral Bus 2

14 References u On the hardware-software partitioning problem: System modeling and partitioning techniques Marisa López-Vallejo, Juan Carlos López July 2003 ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 8 Issue 3 On the hardware-software partitioning problem: System modeling and partitioning techniques On the hardware-software partitioning problem: System modeling and partitioning techniques u A hardware/software partitioner using a dynamically determined granularity Jörg Henkel, Rolf Ernst June 1997 Proceedings of the 34th annual conference on Design automation conference A hardware/software partitioner using a dynamically determined granularity A hardware/software partitioner using a dynamically determined granularity

15 References u Issues in partitioning & design space eploration for codesign: Dynamic hardware/software partitioning: a first approach Greg Stitt, Roman Lysecky, Frank Vahid June 2003 Proceedings of the 40th conference on Design automation Issues in partitioning & design space eploration for codesign: Dynamic hardware/software partitioning: a first approach Issues in partitioning & design space eploration for codesign: Dynamic hardware/software partitioning: a first approach u Hardware/software partitioning of software binaries Greg Stitt, Frank Vahid November 2002 Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design Hardware/software partitioning of software binaries Hardware/software partitioning of software binaries