Logic simulator and fault diagnosis Fan Wang Dept. of Electrical & Computer Engineering Auburn University ELEC7250 Term Project Spring 06’

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Presentation transcript:

Logic simulator and fault diagnosis Fan Wang Dept. of Electrical & Computer Engineering Auburn University ELEC7250 Term Project Spring 06’

Motivations Write a compiler for the hierarchical bench format. Write a logic simulator for combinational circuit Attempt to diagnose the design error

Compiler For hierarchical bench format, the compiler can flatten it Compiler can use flattened netlist to generate the simulation table For convenience, this part is implemented by Matlab. Simulation table Example (generated by matlab) INPUT: 0 INPUT: 1 INPUT: 2 OUTPUT: 15 OUTPUT: 16 Gatetype: XOR Gatename: XOR1 Fanin_List: 2 1 Fanout_List: FA_1_1 /***************************/ Gatetype: AND Gatename: AND1 Fanin_List: 1 2 Fanout_List: FA_1_2 /***************************/ Gatetype: AND Gatename: AND2 Fanin_List: 0 FA_1_1 Fanout_List: FA_1_3 /***************************/ Gatetype: XOR Gatename: XOR2 Fanin_List: FA_1_1 0 Fanout_List: 3 /***************************/

Logic Simulation 1.Read vector to the PI 2.Initialize all the PO, Internal nodes as unknown states (-1). 3.Propagate the value from PI to PO. F or each unknown internal node, search all file until it gets value. If all the PO get value, step 3 end. F or each unknown internal node, search all file until it gets value. If all the PO get value, step 3 end. 4.Repeat 1 to get the next vector. * Implemented by C program

Logic Simulation (Cont.)

Some Comments on logic simulator  The search based algorithm: 1.Time complexity is O( ), N: the number of gates. The worst case is, all gates are list in reverse order. The time complexity is The depth of circuit x The depth of circuit x 2. The levelization of the circuit, the time complexity will the same as the logic simulation based search based algorithm  Better algorithm can be used: link list based algorithm

Diagnosis (Sensitized Path Segmentation + PO trace back) Check PO, see whether the PO get values as expected If error happens: 1. trace back from the error PO to PI to check the paths (PATH 1). 1. trace back from the error PO to PI to check the paths (PATH 1). 2. check which path is sensitized by the vector from PI to PO (PATH 2). 2. check which path is sensitized by the vector from PI to PO (PATH 2). The error is on the path : PATH 1 PATH2 * Not for multiple fault diagnosis

Design error: OR --> AND !! (PI) (PO Good Value) (PO Good Value) (PO Bad Value) (PO Bad Value) V V V V p3 p1 * Based on 4 vectors: error is on p3 p2 p1 Sensitized path segmentation and1 or1 and2 xor1 p2

Thanks!