1 A TATA TBTB TCTC B C A B C (P) Binary Counter using Unclocked T-FF Since a pulse (P) is required to initiate each change of state: T A = BCP, T B = CP, T C = P T C =1 =BC =C

State Graph A B C A + B + C State Table Sequence Generators (Example)

3 A B C A + B + C + T A T B T C x x x x x x x x x Sequence Generators T-FF (Example Cont’d) 1 1 xx A BC 1 1 xx x A BC 1 1 xx x A BC x 1 T A =A’B’+AB =(A’+B)(A+B’) T B =A’C+AB’ =(A’+B')(A+C) T C =(A+B)

4 Sequence Generators (Example Cont’d) Sequence Generator using Clocked T-FF’s Timing Diagram

5 Sequence Generators Example JK-FF’s Logic Diagram State Table

6 A B C A + B + C xx A BC 1 xx 00 0 x A BC 1 1 xx x A BC x D A =A + =B’ D B =B + = A+BC’ D A D B D C Q+ = D Sequence Generator Design with D-FF’s D C =C + = AC’+BC’=C’(A+B)

7 Code Converter using JK-FF’s (shortcut method) BCD to Excess-3

8 Shift Registers Examples of cyclic shift registers. Cyclic-- bits shifted out one end are shifted back into other end rather than being lost. A shift register is a group of FF’s in which a binary number is stored.

9 Understanding the shift operation $85 = $42 = SI = 0 MSBLSB $21 = SI = 0 1st right shift (non- cyclic) 2nd right shift $10 = SI = 0 3rd right shift Etc…. Shifted off end

10 Right Shift vs Left Shift A right shift is MSB to LSB In: D7 D6 D5 D4 D3 D2 D1 D0 SI Out: SIN D7 D6 D5 D4 D3 D2 D1 A left shift is LSB to MSB In: D7 D6 D5 D4 D3 D2 D1 D0 SI Out: D6 D5 D4 D3 D2 D1 D0 SI