Processor Consistency [Goodman 1989]* Processor Consistency is a memory model in which the result of any execution is the same as if the operations of each individual processor appear in program order According to the definition, the order in which writes from two processes occur, as observed by themselves or a third processor need not be identical, but writes issuing from any processor may not be observed in any order other than that in which they are issued. In addition, there must be a unique view of writes to the same location. J. Goodman. Cache consistency and sequential consistency. Technical Report 61, IEEE Scalable Coherent Interface Working Group, Mar (*)

Understanding Processor Consistency Process 1 write x,1 write x,2 Process 2 read x,2 read x,1 Process 1 write x,1 write y,2 Process 2 read y,2 read x,0 Not PC: writes of proc. 1 are seen in different order. Not Coherent: no serialization for X. Not PC: writes of proc. 1 are seen in different order. Coherent.

Understanding Processor Consistency (cont.) PC (despite cyclic dependency). Coherent. Process 1 write x,1 Process 2 read x,1 write y,1 Process 3 read y,1 read x,0 Process 1 write x,1 write z,1 read y,0 Process 2 write y,1 write z,2 read x,0 Not PC. Cannot agree on order of writes to Z. Coherent.

Operational Specification of Memory Models Specifies ordering requirements for supporting a given memory model. Performing a Memory Request: –A read by P i is considered performed with respect to process P k at a point in time when the issuing of a write to the same address by P k can not affect the value returned by the read. –A write by P i is considered performed with respect to process P k at a point in time when an issued read to the same address by P k returns the value defined by this write. –An access is performed when it is performed with respect to all processes.

Operational Specification of Memory Models (cont.) Previous access is an access that appears before the given access in program order of the given process. Gharachorloo et al. gave an operational definition of Processor Consistency. However the memory model they defined, is not comparable with Goodman’s Processor Consistency.

Processor Consistency [Gharachorloo et al. 1990]* Note: reads following a write may bypass the write and perform first (even read of same memory location!). writes (same/different locations) by different processes may be seen by different processes to perform in different orders. Conditions for Processor Consistency: (A)Before a read is allowed to perform with respect to any other process, all previous read accesses must be performed, and (B) Before a write is allowed to perform with respect to any other process, all previous read and write accesses must be performed. K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J.L. Hennessy. Memory consistency and event ordering in scalable shared-memory multiprocessors. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages IEEE, May (*)

Comparing Processor Consistencies Process 1 write x,1 write y,1 Process 2 read y,1 read z,0 Process 3 write z,1 write v,1 Process 4 read v,1 read x,0 According to PC2 no reordering can be made. Therefore, due to the cyclic dependency, no legal PC2 execution is possible ! Denote the Goodman’s PC by PC1 Denote the Gharachorloo et al. PC by PC2 PC1 and PC2 are not comparable. Lets see why. Consider the following example. It is PC1 but not PC2.

Comparing Processor Consistencies (cont.) Consider another example. It is PC2 but not PC1 It is PC2, because according to rule (B) reads can be moved to the beginning at both processes. It is not PC1 because there is no execution in which processes agree on their order of writes to Z. Process 1 write x,1 write z,1 read y,0 Process 2 write y,1 write z,2 read x,0

PRAM Consistency* They often confuse PC with PRAM consistency due to the subtle difference between them. Goodman’s PC (PC1) can be defined as a memory model that is PRAM consistent and in which writes to the same memory location are seen in the same sequential order by all processes. PRAM is a memory model in which writes performed by a single process are seen by all other processes in the order in which they were issued, but writes from different processes may be seen in different orders by different processes. R. J. Lipton and J. S. Sandberg. PRAM: A scalable shared memory. Technical Report , Department of Computer Science, Princeton University, September (*)

PRAM Consistency (cont.) According to the definitions PC1 is stronger then PRAM. The following example is PRAM but no PC1: Process 1 write x,1 read x,2 Process 2 write x,2 read x,1 It is PRAM because both processes see writes of each processors alone in the same order (because there is only one write per process). It is not PC1 because given the constraints imposed by read/write dependencies and program order, the processes can not agree on the order of writes to X.

Causal Consistency* Hard to implement in hardware. Needs graph of dependencies Causal Consistency: Writes that are potentially causally related must be seen by all processes in the same order. Concurrent writes may be seen in a different order on different machines. Weakens sequential consistency by making distinction between events that are potentially causally related and events that are not. M. Ahamad, G. Neiger, P. Kohli, J. Burns, and P. Hutto. Causal Memory: Definitions, Implementation, and Programming. Distributed Computing, 9(1), 93. (*)

Causal Consistency (cont.) Process 1 write x,1 Process 2 write y,1 Process 3 read y,1 read x,0 Process 4 read x,1 read y,0 Causally consistent NOT causally consistent Process 1 write x,1 Process 2 read x,1 write y,1 Process 3 read y,1 read x,0 Process 4 read x,1 read y,0