VHDL Synthesis of a MIPS-32 Processor Bryan Allen Dave Chandler Nate Ransom

Completed Project 5-stage Pipelined MIPS-32 Processor Hazard Detection Data Forwarding Project Goal: Efficient VHDL Coding for Small- Area Synthesis

Subset of Instructions (the full MIPS-32 instruction set will not be implemented) add, addU, addI, addIU and, andI div, divU mult, multU nor, or, ori, xor, xori sll, sra, srl sub, subu lui slt, sltU, sltI, sltIU beq, bgez, bgtz, blez, bltz, bne j, jr lb, lw, lbu sb, sw mfhi, mflo, mthi, mtlo

Dataflow – Pipelining w/o Forwarding

Dataflow - Pipelining with Forwarding

Architecture - Control

Architecture – Pipeline with Forwarding

Architecture - Hazard Detection

Main Components Control Unit Registers and Memory Hazard Detection Unit Forwarding Unit ALU

Simulation Results - 1

Simulation Results - 2

Simulation Results - 3

Synthesis Results

Data Memory Forwarding Unit ALU Hazard Detection Unit Register Bank Sign Extender Control Instruction Memory Program Counter WriteBack Stage Memory Stage Execute Stage Instruction Decode Stage Instruction Fetch Stage CPU (Top Level) Speed (ns)Area(nm 2 )Module

Final Results Violations: None Speed: 200 MHz Area: 896,546 gates Critical Path: Program Counter to Instruction Memory Register ns Max Input Delay: 1 ns Max Output Delay: 0.1 ns Max Input Capacitance: pF Max Output Capacitance: pF

Questions?